From: Segher Boessenkool Date: Tue, 27 Jun 2017 18:24:51 +0000 (+0200) Subject: Backport PRs 61729, 73650, 77850, 80382, 80618, 80692, 80902, 80966 X-Git-Tag: releases/gcc-5.5.0~182 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=098c10ec560aaab5a34c5fee99e6228ab59c3022;p=thirdparty%2Fgcc.git Backport PRs 61729, 73650, 77850, 80382, 80618, 80692, 80902, 80966 Backports from trunk: 2016-08-15 Segher Boessenkool PR rtl-optimization/73650 * lra-constraints.c (simple_move_p): If the insn is multiple_sets it is not a simple move. 2017-01-20 Segher Boessenkool PR target/61729 PR target/77850 * config/rs6000/rs6000.c (rs6000_gimplify_va_arg): Adjust address to read from, for big endian. 2017-04-12 Segher Boessenkool PR target/80382 * config/rs6000/sync.md (atomic_load, atomic_store PR middle-end/80692 * real.c (do_compare): Give decimal_do_compare preference over comparing just the signs. 2017-05-31 Segher Boessenkool PR target/80618 * config/rs6000/vector.md (*vector_uneq): Write the nor in the splitter result in the canonical way. 2017-06-09 Segher Boessenkool PR target/80966 * config/rs6000/rs6000.c (rs6000_emit_allocate_stack): Assert that gen_add3_insn did not fail. * config/rs6000/rs6000.md (add3): If asked to add a constant to r0, construct that number in a temporary reg and add that reg to r0. If asked to put the result in r0 as well, fail. 2017-06-23 Segher Boessenkool PR middle-end/80902 * builtins.c (expand_builtin_atomic_fetch_op): If emitting code after a call, force the call to not be a tail call. gcc/testsuite/ Backports from trunk: 2017-05-17 Segher Boessenkool PR middle-end/80692 * gcc.c-torture/execute/pr80692.c: New testcase. 2017-06-09 Segher Boessenkool PR target/80966 * gcc.target/powerpc/stack-limit.c: New testcase. From-SVN: r249707 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ee8fdc3cb818..ec8b96901b1a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,46 @@ +2017-06-27 Segher Boessenkool + + Backports from trunk: + + 2016-08-15 Segher Boessenkool + PR rtl-optimization/73650 + * lra-constraints.c (simple_move_p): If the insn is multiple_sets + it is not a simple move. + + 2017-01-20 Segher Boessenkool + PR target/61729 + PR target/77850 + * config/rs6000/rs6000.c (rs6000_gimplify_va_arg): Adjust address to + read from, for big endian. + + 2017-04-12 Segher Boessenkool + PR target/80382 + * config/rs6000/sync.md (atomic_load, atomic_store + PR middle-end/80692 + * real.c (do_compare): Give decimal_do_compare preference over + comparing just the signs. + + 2017-05-31 Segher Boessenkool + PR target/80618 + * config/rs6000/vector.md (*vector_uneq): Write the nor in the + splitter result in the canonical way. + + 2017-06-09 Segher Boessenkool + PR target/80966 + * config/rs6000/rs6000.c (rs6000_emit_allocate_stack): Assert that + gen_add3_insn did not fail. + * config/rs6000/rs6000.md (add3): If asked to add a constant to + r0, construct that number in a temporary reg and add that reg to r0. + If asked to put the result in r0 as well, fail. + + 2017-06-23 Segher Boessenkool + PR middle-end/80902 + * builtins.c (expand_builtin_atomic_fetch_op): If emitting code after + a call, force the call to not be a tail call. + 2017-06-23 Thomas Preud'homme Backport from mainline diff --git a/gcc/builtins.c b/gcc/builtins.c index d408c7a53ad1..dedabc4cef4d 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -5594,6 +5594,12 @@ expand_builtin_atomic_fetch_op (machine_mode mode, tree exp, rtx target, gcc_assert (TREE_OPERAND (addr, 0) == fndecl); TREE_OPERAND (addr, 0) = builtin_decl_explicit (ext_call); + /* If we will emit code after the call, the call can not be a tail call. + If it is emitted as a tail call, a barrier is emitted after it, and + then all trailing code is removed. */ + if (!ignore) + CALL_EXPR_TAILCALL (exp) = 0; + /* Expand the call here so we can emit trailing code. */ ret = expand_call (exp, target, ignore); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 8d55c44faf0c..a46729c3f637 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -11525,6 +11525,7 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, size = int_size_in_bytes (type); rsize = (size + 3) / 4; + int pad = 4 * rsize - size; align = 1; if (TARGET_HARD_FLOAT && TARGET_FPRS @@ -11612,6 +11613,10 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, && TYPE_MODE (type) == SDmode) t = fold_build_pointer_plus_hwi (t, size); + /* Args are right-aligned. */ + if (BYTES_BIG_ENDIAN) + t = fold_build_pointer_plus_hwi (t, pad); + gimplify_assign (addr, t, pre_p); gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over)); @@ -11637,6 +11642,11 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_cst (TREE_TYPE (t), -align)); } + + /* Args are right-aligned. */ + if (BYTES_BIG_ENDIAN) + t = fold_build_pointer_plus_hwi (t, pad); + gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); gimplify_assign (unshare_expr (addr), t, pre_p); @@ -22727,9 +22737,11 @@ rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off) && REGNO (stack_limit_rtx) > 1 && REGNO (stack_limit_rtx) <= 31) { - emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size))); - emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, - const0_rtx)); + rtx_insn *insn + = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)); + gcc_assert (insn); + emit_insn (insn); + emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx)); } else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF && TARGET_32BIT diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 6ab47268be5a..ef36cf0b0185 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1504,6 +1504,17 @@ || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (mode)); + /* Adding a constant to r0 is not a valid insn, so use a different + strategy in that case. */ + if (REGNO (operands[1]) == 0 || REGNO (tmp) == 0) + { + if (operands[0] == operands[1]) + FAIL; + rs6000_emit_move (operands[0], operands[2], mode); + emit_insn (gen_add3 (operands[0], operands[1], operands[0])); + DONE; + } + HOST_WIDE_INT val = INTVAL (operands[2]); HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode); diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index 8ba30b986581..b0da0b8b52c3 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -160,8 +160,7 @@ rtx op1 = operands[1]; rtx pti_reg = gen_reg_rtx (PTImode); - // Can't have indexed address for 'lq' - if (indexed_address (XEXP (op1, 0), TImode)) + if (!quad_address_p (XEXP (op1, 0), TImode, false)) { rtx old_addr = XEXP (op1, 0); rtx new_addr = force_reg (Pmode, old_addr); @@ -238,8 +237,7 @@ rtx op1 = operands[1]; rtx pti_reg = gen_reg_rtx (PTImode); - // Can't have indexed address for 'stq' - if (indexed_address (XEXP (op0, 0), TImode)) + if (!quad_address_p (XEXP (op0, 0), TImode, false)) { rtx old_addr = XEXP (op0, 0); rtx new_addr = force_reg (Pmode, old_addr); diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index dd950fa13759..be1a23e456ae 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -480,13 +480,12 @@ (gt:VEC_F (match_dup 2) (match_dup 1))) (set (match_dup 0) - (not:VEC_F (ior:VEC_F (match_dup 3) - (match_dup 4))))] - " + (and:VEC_F (not:VEC_F (match_dup 3)) + (not:VEC_F (match_dup 4))))] { operands[3] = gen_reg_rtx (mode); operands[4] = gen_reg_rtx (mode); -}") +}) (define_insn_and_split "*vector_ltgt" [(set (match_operand:VEC_F 0 "vfloat_operand" "") diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index f4cf6fbc845d..524a143320bd 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -3283,6 +3283,13 @@ simple_move_p (void) lra_assert (curr_insn_set != NULL_RTX); dest = SET_DEST (curr_insn_set); src = SET_SRC (curr_insn_set); + + /* If the instruction has multiple sets we need to process it even if it + is single_set. This can happen if one or more of the SETs are dead. + See PR73650. */ + if (multiple_sets (curr_insn)) + return false; + return ((dclass = get_op_class (dest)) != NO_REGS && (sclass = get_op_class (src)) != NO_REGS /* The backend guarantees that register moves of cost 2 diff --git a/gcc/real.c b/gcc/real.c index 43f124e05f70..93866fdbcd2b 100644 --- a/gcc/real.c +++ b/gcc/real.c @@ -950,12 +950,12 @@ do_compare (const REAL_VALUE_TYPE *a, const REAL_VALUE_TYPE *b, gcc_unreachable (); } - if (a->sign != b->sign) - return -a->sign - -b->sign; - if (a->decimal || b->decimal) return decimal_do_compare (a, b, nan_result); + if (a->sign != b->sign) + return -a->sign - -b->sign; + if (REAL_EXP (a) > REAL_EXP (b)) ret = 1; else if (REAL_EXP (a) < REAL_EXP (b)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index edc247da6c8b..b5155df10676 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2017-06-27 Segher Boessenkool + + Backports from trunk: + + 2017-05-17 Segher Boessenkool + PR middle-end/80692 + * gcc.c-torture/execute/pr80692.c: New testcase. + + 2017-06-09 Segher Boessenkool + PR target/80966 + * gcc.target/powerpc/stack-limit.c: New testcase. + 2017-06-23 Thomas Preud'homme Backport from mainline diff --git a/gcc/testsuite/gcc.c-torture/execute/pr80692.c b/gcc/testsuite/gcc.c-torture/execute/pr80692.c new file mode 100644 index 000000000000..e653c71c9130 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr80692.c @@ -0,0 +1,13 @@ +/* { dg-require-effective-target dfp } */ + +int main () { + _Decimal64 d64 = -0.DD; + + if (d64 != 0.DD) + __builtin_abort (); + + if (d64 != -0.DD) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/stack-limit.c b/gcc/testsuite/gcc.target/powerpc/stack-limit.c new file mode 100644 index 000000000000..e676c96eb8e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/stack-limit.c @@ -0,0 +1,10 @@ +/* { dg-options "-O0 -fstack-limit-register=r14" } */ + +// PR80966 + +int foo (int i) +{ + char arr[135000]; + + arr[i] = 0; +}