From: Cerion Armour-Brown Date: Wed, 16 Feb 2005 18:08:25 +0000 (+0000) Subject: Cleaned up a little more X-Git-Tag: svn/VALGRIND_3_0_1^2~417 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=09d35a8b997355cdbce5d9b007a0452426f9806a;p=thirdparty%2Fvalgrind.git Cleaned up a little more Set Pin_Goto to use GPR3 for the return register (holding next address for dispacher) git-svn-id: svn://svn.valgrind.org/vex/trunk@917 --- diff --git a/VEX/priv/host-ppc32/hdefs.c b/VEX/priv/host-ppc32/hdefs.c index 7ccfe4fedd..1372a2cd08 100644 --- a/VEX/priv/host-ppc32/hdefs.c +++ b/VEX/priv/host-ppc32/hdefs.c @@ -144,7 +144,7 @@ void getAllocableRegs_PPC32 ( Int* nregs, HReg** arr ) { *nregs = 59; *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); - // GPR0 = reserved + // GPR0 = scratch reg where possible - some ops interpret as value zero // GPR1 = stack pointer // GPR2 = TOC pointer (*arr)[ 0] = hregPPC32_GPR3(); @@ -786,7 +786,7 @@ void ppPPC32Instr ( PPC32Instr* i ) ppIRJumpKind(i->Pin.Goto.jk); vex_printf(" ; "); } - vex_printf("bca %s,%%r4, ", showPPC32CondCode(i->Pin.Goto.cond)); + vex_printf("bca %s,%%r3, ", showPPC32CondCode(i->Pin.Goto.cond)); ppPPC32RI(i->Pin.Goto.dst); vex_printf(" ; ret"); if (i->Pin.Goto.cond.test != Pct_ALWAYS) { @@ -1030,9 +1030,8 @@ void getRegUsage_PPC32Instr ( HRegUsage* u, PPC32Instr* i ) /* This is a bit subtle. */ /* First off, claim it trashes all the caller-saved regs which fall within the register allocator's jurisdiction. - These I believe to be: r0,r3:12 + These I believe to be: r3:12 */ - addHRegUse(u, HRmWrite, hregPPC32_GPR0()); addHRegUse(u, HRmWrite, hregPPC32_GPR3()); addHRegUse(u, HRmWrite, hregPPC32_GPR4()); addHRegUse(u, HRmWrite, hregPPC32_GPR5()); @@ -1060,14 +1059,16 @@ void getRegUsage_PPC32Instr ( HRegUsage* u, PPC32Instr* i ) } /* Finally, there is the issue that the insn trashes a register because the literal target address has to be - loaded into a register. %r12 seems a suitable victim. */ + loaded into a register. %r12 seems a suitable victim. + (Can't use %r0, as use ops that interpret it as value zero). */ addHRegUse(u, HRmWrite, hregPPC32_GPR12()); /* Upshot of this is that the assembler really must use %r12, - and no other, as a destination temporary. */ + and no other, as a destination temporary. */ return; case Pin_Goto: addRegUsage_PPC32RI(u, i->Pin.Goto.dst); - addHRegUse(u, HRmWrite, hregPPC32_GPR4()); + /* GPR3 holds destination address from Pin_Goto */ + addHRegUse(u, HRmWrite, hregPPC32_GPR3()); if (i->Pin.Goto.jk != Ijk_Boring) addHRegUse(u, HRmWrite, GuestStatePtr); return; @@ -2080,10 +2081,11 @@ Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i ) case Pin_Call: { Addr32 target; PPC32CondCode cond = i->Pin.Call.cond; - - /* As per detailed comment for Ain_Call in + UInt r_dst = 12; + /* As per detailed comment for Pin_Call in getRegUsage_PPC32Instr above, %r12 is used as an address temporary. */ + /* jump over the following two insns if the condition does not hold */ if (i->Pin.Call.cond.test != Pct_ALWAYS) { @@ -2092,14 +2094,14 @@ Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i ) p = mkFormB(p, invertCondTest(cond.test), cond.flag, target, 1, 0); } - /* addi r12,0,(target & 0xFFFF) - addis r12,r12,((target >> 16) & 0xFFFF) => load target to r12 */ + /* addi r_dst,0,(target & 0xFFFF) + addis r_dst,r_dst,((target >> 16) & 0xFFFF) => load target to r_dst */ target = i->Pin.Call.target; - p = mkFormD(p, 14, 12, 0, (target & 0xFFFF)); - p = mkFormD(p, 15, 12, 12, ((target>>16) & 0xFFFF) ); + p = mkFormD(p, 14, r_dst, 0, (target & 0xFFFF)); + p = mkFormD(p, 15, r_dst, r_dst, ((target>>16) & 0xFFFF) ); - /* mtspr 9,r12 => move r12 to count register */ - p = mkFormXFX(p, 12, 9, 467); + /* mtspr 9,r_dst => move r_dst to count register */ + p = mkFormXFX(p, r_dst, 9, 467); /* bcctrl 20,0 => branch w. link to count register */ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1); @@ -2113,7 +2115,7 @@ Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i ) case Pin_Goto: { UInt magic_num = 0; - UChar r_dst, r_src; + UChar r_dst = 3; /* Put target addr into %r3 */ PPC32CondCode cond = i->Pin.Goto.cond; UInt imm; @@ -2150,10 +2152,7 @@ Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i ) p = mkFormD(p, 14, 31, 0, magic_num); } - - /* Get the destination address into %r4 */ -// CAB: Which reg? On amd64,x86, does 'ret' use rax,eax somehow? - r_dst = 4; + /* Get the destination address into %r3 */ if (i->Pin.Goto.dst->tag == Pri_Imm) { imm = i->Pin.Goto.dst->Pri.Imm.imm32; if (imm < 0x10000) { @@ -2167,9 +2166,9 @@ Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i ) } } else { vassert(i->Pin.Goto.dst->tag == Pri_Reg); - if (i->Pin.Goto.dst->Pri.Reg.reg != hregPPC32_GPR4()) { + UChar r_src = iregNo(i->Pin.Goto.dst->Pri.Reg.reg); + if (r_dst != r_src) { /* add r_dst, 0, r_src */ - r_src = iregNo(i->Pin.Goto.dst->Pri.Reg.reg); p = mkFormXO(p, 31, r_dst, 0, r_src, 0, 266, 0); } } @@ -2263,8 +2262,7 @@ Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32Instr* i ) p = mkFormD(p, 14, r_dst, 0, 1); } else { rot_imm = 1 + cond.flag; - r_tmp = 1; -// CAB: how choose r_tmp so don't kill anything else? + r_tmp = 0; // Not within scope of regalloc, so no need to declare. // r_tmp = CR => mfcr r_tmp p = mkFormX(p, 31, r_tmp, 0, 0, 19, 0); diff --git a/VEX/priv/host-ppc32/hdefs.h b/VEX/priv/host-ppc32/hdefs.h index 5359103dc9..9a991e0e84 100644 --- a/VEX/priv/host-ppc32/hdefs.h +++ b/VEX/priv/host-ppc32/hdefs.h @@ -133,47 +133,10 @@ typedef Pcf_SO = 3, /* summary overflow */ // field 6 (floating point only) - Pcf_FX = 4, /* neg | lt */ - Pcf_FEX = 5, /* pos | gt */ - Pcf_VX = 6, /* zero | equal */ - Pcf_OX = 7, /* summary overflow */ -#if 0 - // field 5 - Pcf_f5_LT = 8, /* neg | lt */ - Pcf_f5_GT = 9, /* pos | gt */ - Pcf_f5_EQ = 10, /* zero | equal */ - Pcf_f5_SO = 11, /* summary overflow */ - - // field 4 - Pcf_f4_LT = 12, /* neg | lt */ - Pcf_f4_GT = 13, /* pos | gt */ - Pcf_f4_EQ = 14, /* zero | equal */ - Pcf_f4_SO = 15, /* summary overflow */ - - // field 3 - Pcf_f3_LT = 16, /* neg | lt */ - Pcf_f3_GT = 17, /* pos | gt */ - Pcf_f3_EQ = 18, /* zero | equal */ - Pcf_f3_SO = 19, /* summary overflow */ - - // field 2 - Pcf_f2_LT = 20, /* neg | lt */ - Pcf_f2_GT = 21, /* pos | gt */ - Pcf_f2_EQ = 22, /* zero | equal */ - Pcf_f2_SO = 23, /* summary overflow */ - - // field 1 - Pcf_f1_LT = 24, /* neg | lt */ - Pcf_f1_GT = 25, /* pos | gt */ - Pcf_f1_EQ = 26, /* zero | equal */ - Pcf_f1_SO = 27, /* summary overflow */ - - // field 0 - Pcf_f0_LT = 28, /* neg | lt */ - Pcf_f0_GT = 29, /* pos | gt */ - Pcf_f0_EQ = 30, /* zero | equal */ - Pcf_f0_SO = 31, /* summary overflow */ -#endif + Pcf_FX = 4, /* neg | lt */ + Pcf_FEX = 5, /* pos | gt */ + Pcf_VX = 6, /* zero | equal */ + Pcf_OX = 7, /* summary overflow */ } PPC32CondFlag; diff --git a/VEX/priv/host-ppc32/isel.c b/VEX/priv/host-ppc32/isel.c index 5c51b38c3f..f17047082e 100644 --- a/VEX/priv/host-ppc32/isel.c +++ b/VEX/priv/host-ppc32/isel.c @@ -62,7 +62,8 @@ GPR3:12 Caller-saved regs GPR14:30 Callee-saved regs - GPR3:10 Parameter-carrying regs + GPR3 [Return | Parameter] - carrying reg + GPR4:10 Parameter-carrying regs Floating Point Regs @@ -1279,8 +1280,9 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) /* Marshal args, do the call, clear stack. */ doHelperCall( env, False, NULL, e->Iex.CCall.cee, e->Iex.CCall.args ); - - addInstr(env, mk_iMOVds_RR(dst, hregPPC32_GPR4())); + + /* GPR3 now holds the destination address from Pin_Goto */ + addInstr(env, mk_iMOVds_RR(dst, hregPPC32_GPR3())); return dst; }