From: Zephyr Li Date: Tue, 16 Jun 2026 07:56:48 +0000 (+0800) Subject: lscpu: riscv: preserve ISA extension order X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=09d85523054f242072c98cba0ec0c62dfe26fb35;p=thirdparty%2Futil-linux.git lscpu: riscv: preserve ISA extension order The Linux RISC-V UABI defines the canonical ISA string order in /proc/cpuinfo. Do not sort multi-letter extensions alphabetically in lscpu; keep the kernel-provided order and only replace separators for display. --- diff --git a/sys-utils/lscpu-riscv.c b/sys-utils/lscpu-riscv.c index 3d0176206..f49aa3be4 100644 --- a/sys-utils/lscpu-riscv.c +++ b/sys-utils/lscpu-riscv.c @@ -14,11 +14,6 @@ #include "strv.h" #include "cctype.h" -static int riscv_cmp_func(const void *a, const void *b) -{ - return strcmp(*(const char **)a, *(const char **)b); -} - bool is_riscv(struct lscpu_cputype *ct) { const char *base_isa[] = {"rv32", "rv64", "rv128"}; @@ -42,11 +37,7 @@ void lscpu_format_isa_riscv(struct lscpu_cputype *ct) split = ul_strv_split(ct->isa, "_"); - /* Sort multi-letter extensions alphabetically */ - if (ul_strv_length(split) > 1) - qsort(&split[1], ul_strv_length(split) - 1, sizeof(char *), riscv_cmp_func); - - /* Keep Base ISA and single-letter extensions at the start */ + /* Keep the kernel-provided ISA extension order. */ strcpy(ct->isa, split[0]); for (i = 1; i < ul_strv_length(split); i++) { diff --git a/tests/expected/lscpu/lscpu-rv64-visionfive2 b/tests/expected/lscpu/lscpu-rv64-visionfive2 index 762d7216b..8997a1769 100644 --- a/tests/expected/lscpu/lscpu-rv64-visionfive2 +++ b/tests/expected/lscpu/lscpu-rv64-visionfive2 @@ -8,7 +8,7 @@ Model: 0x4210427 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 -ISA: rv64imafdc zba zbb zicntr zicsr zifencei zihpm +ISA: rv64imafdc zicntr zicsr zifencei zihpm zba zbb MMU: sv39 L1d cache: 128 KiB (4 instances) L1i cache: 128 KiB (4 instances)