From: Thomas Preud'homme Date: Mon, 20 Nov 2017 11:06:05 +0000 (+0000) Subject: [ARM] Do no clobber r4 in Armv8-M nonsecure call X-Git-Tag: basepoints/gcc-9~3208 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0a413fbc6c7482c670fcf471dc3ecf2d50250a51;p=thirdparty%2Fgcc.git [ARM] Do no clobber r4 in Armv8-M nonsecure call Expanders for Armv8-M nonsecure call unnecessarily clobber r4 despite the libcall they perform not writing to r4. Furthermore, the requirement for the branch target address to be in r4 as expected by the libcall is modeled in a convoluted way in the define_insn patterns: the address is a register match_operand constrained by the match_dup for the clobber which is guaranteed to be r4 due to the expander. This patch simplifies all this by simply requiring the address to be in r4 and removing the clobbers. Expanders are left alone because cmse_nonsecure_call_clear_caller_saved relies on branch target memory attributes which would be lost if expanding to reg:SI R4_REGNUM. 2017-11-20 Thomas Preud'homme gcc/ * config/arm/arm.md (R4_REGNUM): Define constant. (nonsecure_call_internal): Remove r4 clobber. (nonsecure_call_value_internal): Likewise. * config/arm/thumb1.md (nonsecure_call_reg_thumb1_v5): Remove second clobber and resequence match_operands. (nonsecure_call_value_reg_thumb1_v5): Likewise. * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Likewise. (nonsecure_call_value_reg_thumb2): Likewise. From-SVN: r254950 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 48f87abfd977..4df4d801854b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2017-11-20 Thomas Preud'homme + + * config/arm/arm.md (R4_REGNUM): Define constant. + (nonsecure_call_internal): Remove r4 clobber. + (nonsecure_call_value_internal): Likewise. + * config/arm/thumb1.md (nonsecure_call_reg_thumb1_v5): Remove second + clobber and resequence match_operands. + (nonsecure_call_value_reg_thumb1_v5): Likewise. + * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Likewise. + (nonsecure_call_value_reg_thumb2): Likewise. + 2017-11-20 Jakub Jelinek PR tree-optimization/78821 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index fd3aebd428a4..545ee257699a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -30,6 +30,7 @@ (define_constants [(R0_REGNUM 0) ; First CORE register (R1_REGNUM 1) ; Second CORE register + (R4_REGNUM 4) ; Fifth CORE register (IP_REGNUM 12) ; Scratch register (SP_REGNUM 13) ; Stack pointer (LR_REGNUM 14) ; Return address register @@ -8072,14 +8073,13 @@ UNSPEC_NONSECURE_MEM) (match_operand 1 "general_operand" "")) (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM)) - (clobber (reg:SI 4))])] + (clobber (reg:SI LR_REGNUM))])] "use_cmse" " { rtx tmp; tmp = copy_to_suggested_reg (XEXP (operands[0], 0), - gen_rtx_REG (SImode, 4), + gen_rtx_REG (SImode, R4_REGNUM), SImode); operands[0] = replace_equiv_address (operands[0], tmp); @@ -8164,14 +8164,13 @@ UNSPEC_NONSECURE_MEM) (match_operand 2 "general_operand" ""))) (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM)) - (clobber (reg:SI 4))])] + (clobber (reg:SI LR_REGNUM))])] "use_cmse" " { rtx tmp; tmp = copy_to_suggested_reg (XEXP (operands[1], 0), - gen_rtx_REG (SImode, 4), + gen_rtx_REG (SImode, R4_REGNUM), SImode); operands[1] = replace_equiv_address (operands[1], tmp); diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 5d196a673355..f91659386bf2 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -1732,12 +1732,11 @@ ) (define_insn "*nonsecure_call_reg_thumb1_v5" - [(call (unspec:SI [(mem:SI (match_operand:SI 0 "register_operand" "l*r"))] + [(call (unspec:SI [(mem:SI (reg:SI R4_REGNUM))] UNSPEC_NONSECURE_MEM) - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM)) - (clobber (match_dup 0))] + (match_operand 0 "" "")) + (use (match_operand 1 "" "")) + (clobber (reg:SI LR_REGNUM))] "TARGET_THUMB1 && use_cmse && !SIBLING_CALL_P (insn)" "bl\\t__gnu_cmse_nonsecure_call" [(set_attr "length" "4") @@ -1779,12 +1778,11 @@ (define_insn "*nonsecure_call_value_reg_thumb1_v5" [(set (match_operand 0 "" "") (call (unspec:SI - [(mem:SI (match_operand:SI 1 "register_operand" "l*r"))] + [(mem:SI (reg:SI R4_REGNUM))] UNSPEC_NONSECURE_MEM) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM)) - (clobber (match_dup 1))] + (match_operand 1 "" ""))) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] "TARGET_THUMB1 && use_cmse" "bl\\t__gnu_cmse_nonsecure_call" [(set_attr "length" "4") diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index abe90d4f4e45..60f71c768adb 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -552,12 +552,11 @@ ) (define_insn "*nonsecure_call_reg_thumb2" - [(call (unspec:SI [(mem:SI (match_operand:SI 0 "s_register_operand" "r"))] + [(call (unspec:SI [(mem:SI (reg:SI R4_REGNUM))] UNSPEC_NONSECURE_MEM) - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM)) - (clobber (match_dup 0))] + (match_operand 0 "" "")) + (use (match_operand 1 "" "")) + (clobber (reg:SI LR_REGNUM))] "TARGET_THUMB2 && use_cmse" "bl\\t__gnu_cmse_nonsecure_call" [(set_attr "length" "4") @@ -578,12 +577,11 @@ (define_insn "*nonsecure_call_value_reg_thumb2" [(set (match_operand 0 "" "") (call - (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "l*r"))] + (unspec:SI [(mem:SI (reg:SI R4_REGNUM))] UNSPEC_NONSECURE_MEM) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM)) - (clobber (match_dup 1))] + (match_operand 1 "" ""))) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] "TARGET_THUMB2 && use_cmse" "bl\t__gnu_cmse_nonsecure_call" [(set_attr "length" "4")