From: Pan Li <pan2.li@intel.com>
Date: Thu, 6 Mar 2025 01:24:18 +0000 (+0800)
Subject: RISC-V: Tweak asm check for test case multiple_rgroup_zbb.c
X-Git-Tag: basepoints/gcc-16~1705
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0aa9b079aec260b120b7c9fdba8c21066425c73d;p=thirdparty%2Fgcc.git

RISC-V: Tweak asm check for test case multiple_rgroup_zbb.c

The changes to vsetvl pass since 14 result in the asm check failure,
update the asm check to meet the newest behavior.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Tweak
	the asm check for vsetvl.

Signed-off-by: Pan Li <pan2.li@intel.com>
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
index a851229daacf..a6d4b77ccd72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
@@ -20,4 +20,7 @@ test (uint16_t *__restrict f, uint32_t *__restrict d, uint64_t *__restrict e,
     }
 }
 
-/* { dg-final { scan-assembler-times "vsetvli\tzero,\s*\[a-z0-9\]+,\s*e16,\s*m1,\s*ta,\s*ma" 4 } } */
+/* { dg-final { scan-assembler-times "vsetvli\tzero,\s*\[a-z0-9\]+,\s*e16,\s*m\[1248\],\s*ta,\s*ma" 1 } } */
+/* { dg-final { scan-assembler-times "vsetvli\tzero,\s*\[a-z0-9\]+,\s*e32,\s*m\[1248\],\s*ta,\s*ma" 1 } } */
+/* { dg-final { scan-assembler-times "vsetvli\tzero,\s*\[a-z0-9\]+,\s*e64,\s*m\[1248\],\s*ta,\s*ma" 1 } } */
+/* { dg-final { scan-assembler-times "vsetivli\tzero,\s*\[0-9\]+,\s*e64,\s*m\[1248\],\s*ta,\s*ma" 1 } } */