From: Cristian Ciocaltea Date: Mon, 27 Apr 2026 21:57:27 +0000 (+0300) Subject: arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-roc-pc X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0c58a27bf04d88c979dc8ce86c62bb13d15626e4;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-roc-pc The board exposes the GPIO4_B2 line to control the voltage bias on the HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. While at it, move hym8563 down to fix the ordering of &pinctrl entries. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-9-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner --- diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts index 7e179862da6e5..aa02cf510d6db 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts @@ -224,6 +224,10 @@ }; &hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -367,9 +371,9 @@ }; &pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + hdmi { + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -379,6 +383,12 @@ }; }; + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + leds { led_pins: led-pins { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,