From: Nathan Moinvaziri Date: Sat, 14 Mar 2020 04:15:50 +0000 (-0600) Subject: Apply compiler flags only to source files that require them in CMake. X-Git-Tag: 1.9.9-b1~176 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0cab92e7faa5fb05bafd9c587918158cc933ed1d;p=thirdparty%2Fzlib-ng.git Apply compiler flags only to source files that require them in CMake. --- diff --git a/CMakeLists.txt b/CMakeLists.txt index 020da4aa..9510a235 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -640,21 +640,14 @@ if(WITH_INFLATE_ALLOW_INVALID_DIST) endif() # -# Macro to add either the given intrinsics option to the global compiler options, +# Macro to add the given intrinsics option to the specified files, # or ${NATIVEFLAG} (-march=native) if that is appropriate and possible. -# An alternative version of this macro would take a file argument, and set ${flag} -# only for that file as opposed to ${NATIVEFLAG} globally, to limit side-effect of -# using ${flag} globally. # macro(add_intrinsics_option flag) if(WITH_NATIVE_INSTRUCTIONS AND NATIVEFLAG) - if(NOT "${CMAKE_C_FLAGS} " MATCHES ".*${NATIVEFLAG} .*") - set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${NATIVEFLAG}") - endif() + set_property(SOURCE ${ARGN} PROPERTY COMPILE_FLAGS ${NATIVEFLAG}) else() - if(NOT "${CMAKE_C_FLAGS} " MATCHES ".*${flag} .*") - set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${flag}") - endif() + set_property(SOURCE ${ARGN} PROPERTY COMPILE_FLAGS ${flag}) endif() endmacro() @@ -682,9 +675,10 @@ if(WITH_OPTIM) list(APPEND ZLIB_ARCH_HDRS ${ARCHDIR}/arm.h) list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/armfeature.c) if(WITH_NEON) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/adler32_neon.c ${ARCHDIR}/slide_neon.c) add_definitions(-DARM_NEON_ADLER32 -DARM_NEON_SLIDEHASH) - add_intrinsics_option("${NEONFLAG}") + set(NEON_SRCS ${ARCHDIR}/adler32_neon.c ${ARCHDIR}/slide_neon.c) + list(APPEND ZLIB_ARCH_SRCS ${NEON_SRCS}) + add_intrinsics_option("${NEONFLAG}" ${NEON_SRCS}) if(MSVC) add_definitions(-D__ARM_NEON__) endif() @@ -692,12 +686,13 @@ if(WITH_OPTIM) add_feature_info(NEON_SLIDEHASH 1 "Support NEON instructions in slide_hash, using \"${NEONFLAG}\"") endif() if(WITH_ACLE) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/crc32_acle.c ${ARCHDIR}/insert_string_acle.c) add_definitions(-DARM_ACLE_CRC_HASH) + set(ACLE_SRCS ${ARCHDIR}/crc32_acle.c ${ARCHDIR}/insert_string_acle.c) # For ARM aarch64, we need to check WITH_NEON first if("${ARCH}" MATCHES "arm" OR NOT WITH_NEON) - add_intrinsics_option("${ACLEFLAG}") + add_intrinsics_option("${ACLEFLAG}" ${ACLE_SRCS}) endif() + list(APPEND ZLIB_ARCH_SRCS ${ACLE_SRCS}) add_feature_info(ACLE_CRC 1 "Support ACLE optimized CRC hash generation, using \"${ACLEFLAG}\"") endif() elseif(BASEARCH_PPC_FOUND) @@ -706,14 +701,11 @@ if(WITH_OPTIM) add_definitions(-DPOWER_FEATURES) add_definitions(-DPOWER8_VSX_ADLER32) add_definitions(-DPOWER8_VSX_SLIDEHASH) - set(ZLIB_POWER8_SRCS - ${ARCHDIR}/adler32_power8.c - ${ARCHDIR}/slide_hash_power8.c) - set_source_files_properties( - ${ZLIB_POWER8_SRCS} - PROPERTIES COMPILE_FLAGS ${POWER8FLAG}) list(APPEND ZLIB_ARCH_HDRS ${ARCHDIR}/power.h) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/power.c ${ZLIB_POWER8_SRCS}) + list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/power.c) + set(POWER8_SRCS ${ARCHDIR}/adler32_power8.c ${ARCHDIR}/slide_hash_power8.c) + list(APPEND ZLIB_ARCH_SRCS ${POWER8_SRCS}) + add_intrinsics_option("${POWER8FLAG}" ${POWER8_SRCS}) endif() elseif(BASEARCH_S360_FOUND AND "${ARCH}" MATCHES "s390x") if(WITH_DFLTCC_DEFLATE OR WITH_DFLTCC_INFLATE) @@ -737,32 +729,38 @@ if(WITH_OPTIM) endif() if(WITH_AVX2 AND HAVE_AVX2_INTRIN) add_definitions(-DX86_AVX2 -DX86_AVX2_ADLER32) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/slide_avx.c ${ARCHDIR}/adler32_avx.c) + set(AVX2_SRCS ${ARCHDIR}/slide_avx.c) add_feature_info(AVX2_SLIDEHASH 1 "Support AVX2 optimized slide_hash, using \"${AVX2FLAG}\"") - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/compare258_avx.c) + list(APPEND AVX2_SRCS ${ARCHDIR}/compare258_avx.c) add_feature_info(AVX2_COMPARE258 1 "Support AVX2 optimized compare258, using \"${AVX2FLAG}\"") + list(APPEND AVX2_SRCS ${ARCHDIR}/adler32_avx.c) add_feature_info(AVX2_ADLER32 1 "Support AVX2-accelerated adler32, using \"${AVX2FLAG}\"") - add_intrinsics_option("${AVX2FLAG}") + list(APPEND ZLIB_ARCH_SRCS ${AVX2_SRCS}) + add_intrinsics_option("${AVX2FLAG}" ${AVX2_SRCS}) endif() if(WITH_SSE4 AND (HAVE_SSE42CRC_INLINE_ASM OR HAVE_SSE42CRC_INTRIN)) add_definitions(-DX86_SSE42_CRC_HASH) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/insert_string_sse.c) + set(SSE42_SRCS ${ARCHDIR}/insert_string_sse.c) add_feature_info(SSE42_CRC 1 "Support SSE4.2 optimized CRC hash generation, using \"${SSE4FLAG}\"") - add_intrinsics_option("${SSE4FLAG}") + list(APPEND ZLIB_ARCH_SRCS ${SSE42_SRCS}) + add_intrinsics_option("${SSE4FLAG}" ${SSE42_SRCS}) if(HAVE_SSE42CRC_INTRIN) add_definitions(-DX86_SSE42_CRC_INTRIN) endif() endif() if(HAVE_SSE42CMPSTR_INTRIN) add_definitions(-DX86_SSE42_CMP_STR) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/compare258_sse.c) + set(SSE42_SRCS ${ARCHDIR}/compare258_sse.c) add_feature_info(SSE42_COMPARE258 1 "Support SSE4.2 optimized compare258, using \"${SSE4FLAG}\"") + list(APPEND ZLIB_ARCH_SRCS ${SSE42_SRCS}) + add_intrinsics_option("${SSE4FLAG}" ${SSE42_SRCS}) endif() if(WITH_SSE2 AND HAVE_SSE2_INTRIN) add_definitions(-DX86_SSE2) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/slide_sse.c) + set(SSE2_SRCS ${ARCHDIR}/slide_sse.c) + list(APPEND ZLIB_ARCH_SRCS ${SSE2_SRCS}) if(NOT ${ARCH} MATCHES "x86_64") - add_intrinsics_option("${SSE2FLAG}") + add_intrinsics_option("${SSE2FLAG}" ${SSE2_SRCS}) add_feature_info(FORCE_SSE2 FORCE_SSE2 "Assume CPU is SSE2 capable") if(FORCE_SSE2) add_definitions(-DX86_NOCHECK_SSE2) @@ -771,14 +769,16 @@ if(WITH_OPTIM) endif() if(WITH_SSSE3 AND HAVE_SSSE3_INTRIN) add_definitions(-DX86_SSSE3 -DX86_SSSE3_ADLER32) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/adler32_ssse3.c) + set(SSSE3_SRCS ${ARCHDIR}/adler32_ssse3.c) add_feature_info(SSSE3_ADLER32 1 "Support SSSE3-accelerated adler32, using \"${SSSE3FLAG}\"") - add_intrinsics_option("${SSSE3FLAG}") + list(APPEND ZLIB_ARCH_SRCS ${SSSE3_SRCS}) + add_intrinsics_option("${SSSE3FLAG}" ${SSSE3_SRCS}) endif() if(WITH_PCLMULQDQ AND HAVE_PCLMULQDQ_INTRIN) add_definitions(-DX86_PCLMULQDQ_CRC) - list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/crc_folding.c) - add_intrinsics_option("${PCLMULFLAG}") + set(PCLMULQDQ_SRCS ${ARCHDIR}/crc_folding.c) + list(APPEND ZLIB_ARCH_SRCS ${PCLMULQDQ_SRCS}) + add_intrinsics_option("${SSE4FLAG} ${PCLMULFLAG}" ${PCLMULQDQ_SRCS}) if(HAVE_SSE42CRC_INLINE_ASM) add_feature_info(PCLMUL_CRC 1 "Support CRC hash generation using PCLMULQDQ, using \"${PCLMULFLAG}\"") else() diff --git a/arch/arm/adler32_neon.c b/arch/arm/adler32_neon.c index a6e87904..adda6f61 100644 --- a/arch/arm/adler32_neon.c +++ b/arch/arm/adler32_neon.c @@ -4,7 +4,7 @@ * * For conditions of distribution and use, see copyright notice in zlib.h */ -#if defined(__ARM_NEON__) || defined(__ARM_NEON) +#ifdef ARM_NEON_ADLER32 #ifdef _M_ARM64 # include #else diff --git a/arch/arm/crc32_acle.c b/arch/arm/crc32_acle.c index 54060354..768c22ba 100644 --- a/arch/arm/crc32_acle.c +++ b/arch/arm/crc32_acle.c @@ -5,7 +5,7 @@ * */ -#ifdef __ARM_FEATURE_CRC32 +#ifdef ARM_ACLE_CRC_HASH # include # ifdef ZLIB_COMPAT # include diff --git a/arch/arm/insert_string_acle.c b/arch/arm/insert_string_acle.c index 28345d8a..2fdbe6ff 100644 --- a/arch/arm/insert_string_acle.c +++ b/arch/arm/insert_string_acle.c @@ -5,7 +5,7 @@ * */ -#if defined(__ARM_FEATURE_CRC32) && defined(ARM_ACLE_CRC_HASH) +#ifdef ARM_ACLE_CRC_HASH #include #include "../../zbuild.h" #include "../../deflate.h" diff --git a/functable.c b/functable.c index a9d5f554..d8fcd312 100644 --- a/functable.c +++ b/functable.c @@ -44,7 +44,7 @@ void slide_hash_avx2(deflate_state *s); /* adler32 */ extern uint32_t adler32_c(uint32_t adler, const unsigned char *buf, size_t len); -#if (defined(__ARM_NEON__) || defined(__ARM_NEON)) && defined(ARM_NEON_ADLER32) +#ifdef ARM_NEON_ADLER32 extern uint32_t adler32_neon(uint32_t adler, const unsigned char *buf, size_t len); #endif #ifdef X86_SSSE3_ADLER32 @@ -60,7 +60,7 @@ extern uint32_t adler32_power8(uint32_t adler, const unsigned char* buf, size_t /* CRC32 */ ZLIB_INTERNAL uint32_t crc32_generic(uint32_t, const unsigned char *, uint64_t); -#ifdef __ARM_FEATURE_CRC32 +#ifdef ARM_ACLE_CRC_HASH extern uint32_t crc32_acle(uint32_t, const unsigned char *, uint64_t); #endif @@ -147,7 +147,7 @@ ZLIB_INTERNAL Pos insert_string_stub(deflate_state *const s, const Pos str, unsi #ifdef X86_SSE42_CRC_HASH if (x86_cpu_has_sse42) functable.insert_string = &insert_string_sse4; -#elif defined(__ARM_FEATURE_CRC32) && defined(ARM_ACLE_CRC_HASH) +#elif defined(ARM_ACLE_CRC_HASH) if (arm_cpu_has_crc32) functable.insert_string = &insert_string_acle; #endif @@ -161,7 +161,7 @@ ZLIB_INTERNAL Pos quick_insert_string_stub(deflate_state *const s, const Pos str #ifdef X86_SSE42_CRC_HASH if (x86_cpu_has_sse42) functable.quick_insert_string = &quick_insert_string_sse4; -#elif defined(__ARM_FEATURE_CRC32) && defined(ARM_ACLE_CRC_HASH) +#elif defined(ARM_ACLE_CRC_HASH) if (arm_cpu_has_crc32) functable.quick_insert_string = &quick_insert_string_acle; #endif @@ -202,7 +202,7 @@ ZLIB_INTERNAL uint32_t adler32_stub(uint32_t adler, const unsigned char *buf, si functable.adler32 = &adler32_c; cpu_check_features(); -#if (defined(__ARM_NEON__) || defined(__ARM_NEON)) && defined(ARM_NEON_ADLER32) +#ifdef ARM_NEON_ADLER32 # ifndef ARM_NOCHECK_NEON if (arm_cpu_has_neon) # endif @@ -235,7 +235,7 @@ ZLIB_INTERNAL uint32_t crc32_stub(uint32_t crc, const unsigned char *buf, uint64 if (sizeof(void *) == sizeof(ptrdiff_t)) { #if BYTE_ORDER == LITTLE_ENDIAN functable.crc32 = crc32_little; -# if defined(__ARM_FEATURE_CRC32) && defined(ARM_ACLE_CRC_HASH) +# if defined(ARM_ACLE_CRC_HASH) if (arm_cpu_has_crc32) functable.crc32 = crc32_acle; # endif