From: Dave Jiang <dave.jiang@intel.com>
Date: Mon, 2 Feb 2026 16:39:41 +0000 (-0700)
Subject: Merge branch 'for-7.0/cxl-aer-prep' into cxl-for-next
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0da3050bdded5f121aaca6b5247ea50681d7129e;p=thirdparty%2Fkernel%2Flinux.git

Merge branch 'for-7.0/cxl-aer-prep' into cxl-for-next

Fixup and refactor downstream port enumeration to prepare for CXL port
protocol error handling. Main motivation is to move endpoint
component register mapping to a port object.

cxl/port: Unify endpoint and switch port lookup
cxl/port: Move endpoint component register management to cxl_port
cxl/port: Map Port RAS registers
cxl/port: Move dport RAS setup to dport add time
cxl/port: Move dport probe operations to a driver event
cxl/port: Move decoder setup before dport creation
cxl/port: Cleanup dport removal with a devres group
cxl/port: Reduce number of @dport variables in cxl_port_add_dport()
cxl/port: Cleanup handling of the nr_dports 0 -> 1 transition
---

0da3050bdded5f121aaca6b5247ea50681d7129e
diff --cc drivers/cxl/port.c
index 7937e7e53797c,0ae78469207a3..ada51948d52fa
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@@ -154,9 -275,9 +275,10 @@@ static struct cxl_dport *cxl_port_add_d
  static struct cxl_driver cxl_port_driver = {
  	.name = "cxl_port",
  	.probe = cxl_port_probe,
+ 	.add_dport = cxl_port_add_dport,
  	.id = CXL_DEVICE_PORT,
  	.drv = {
 +		.probe_type = PROBE_FORCE_SYNCHRONOUS,
  		.dev_groups = cxl_port_attribute_groups,
  	},
  };