From: Alireza Sanaee Date: Thu, 23 Apr 2026 09:24:09 +0000 (+0100) Subject: target/arm/tcg: increase cache level for cpu=max X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0dc85587be2edc7cdeaeebed4723b53c68a7e57d;p=thirdparty%2Fqemu.git target/arm/tcg: increase cache level for cpu=max This patch addresses cache description in the `aarch64_max_tcg_initfn` function for cpu=max. It introduces three levels of caches and modifies the cache description registers accordingly. Reviewed-by: Gustavo Romero Reviewed-by: Jonathan Cameron Signed-off-by: Alireza Sanaee Message-id: 20260311160609.358-2-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell --- diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 84857fb706d..649d854a65b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1167,6 +1167,16 @@ void aarch64_max_tcg_initfn(Object *obj) uint64_t t; uint32_t u; + SET_IDREG(isar, CLIDR, 0x8200123); + /* 64KB L1 dcache */ + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); + /* 1MB L2 unified cache */ + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); + /* 2MB L3 unified cache */ + cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); + /* * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default * to because we started with aarch64_a57_initfn(). A 'max' CPU might