From: Sunil Khatri Date: Tue, 13 Aug 2024 17:04:26 +0000 (+0530) Subject: drm/amdgpu: remove ME0 registers from mi300 dump X-Git-Tag: v6.12-rc1~126^2~17^2~84 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0f2c243dbfa008cec2dad03ea074156b6b176a03;p=thirdparty%2Fkernel%2Flinux.git drm/amdgpu: remove ME0 registers from mi300 dump Remove ME0 registers from MI300 gfx_9_4_3 ipdump MI300 does not have gfx ME and hence those register are just empty one and could be dropped. Signed-off-by: Sunil Khatri Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index dd146322f2095..619ff3ec2c863 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -75,42 +75,11 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB2_BASE), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB2_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB2_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB1_CMD_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB2_CMD_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB1_BASE_LO), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB1_BASE_HI), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB1_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB2_BASE_LO), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB2_BASE_HI), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB2_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), - SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), - SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_CNTL), - SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), @@ -122,11 +91,8 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_INSTR_PNTR), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), @@ -139,11 +105,8 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), /* cp header registers */ - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_HEADER_DUMP), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), - SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), - SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), /* SE status registers */ SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),