From: Philippe Mathieu-Daudé Date: Thu, 24 Apr 2025 20:24:06 +0000 (+0200) Subject: target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c X-Git-Tag: v10.1.0-rc0~104^2~41 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0f81774dd1c19de5dedb3c8f2d74e5b9a73d8c12;p=thirdparty%2Fqemu.git target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c "accel/tcg/getpc.h" is pulled in indirectly. Include it explicitly to avoid when refactoring unrelated headers: target/riscv/csr.c:2117:25: error: call to undeclared function 'GETPC' [-Wimplicit-function-declaration] 2117 | if ((val & RVC) && (GETPC() & ~3) != 0) { | ^ Note the TODO comment around GETPC() added upon introduction in commit f18637cd611 ("RISC-V: Add misa runtime write support"): 2099 static RISCVException write_misa(CPURISCVState *env, int csrno, 2100 target_ulong val) 2101 { ... 2113 /* 2114 * Suppress 'C' if next instruction is not aligned 2115 * TODO: this should check next_pc 2116 */ 2117 if ((val & RVC) && (GETPC() & ~3) != 0) { 2118 val &= ~RVC; 2119 } Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Acked-by: Alistair Francis Signed-off-by: Richard Henderson Message-ID: <20250424202412.91612-8-philmd@linaro.org> --- diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c52c87faaea..13086438552 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -28,6 +28,7 @@ #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/icount.h" +#include "accel/tcg/getpc.h" #include "qemu/guest-random.h" #include "qapi/error.h" #include