From: Richard Henderson Date: Wed, 8 Oct 2025 21:55:28 +0000 (-0700) Subject: target/arm: Introduce regime_to_gcs X-Git-Tag: v10.2.0-rc1~67^2~48 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0fe292fadb4d1886ad57bb14abcfb4130901b0f6;p=thirdparty%2Fqemu.git target/arm: Introduce regime_to_gcs Add a lookup from any a64 mmu index to the gcs mmu index within the same translation regime. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20251008215613.300150-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index f494ec348d..962b053852 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -21,6 +21,7 @@ FIELD(MMUIDXINFO, USER, 8, 1) FIELD(MMUIDXINFO, STAGE1, 9, 1) FIELD(MMUIDXINFO, STAGE2, 10, 1) FIELD(MMUIDXINFO, GCS, 11, 1) +FIELD(MMUIDXINFO, TG, 12, 5) extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; @@ -100,4 +101,13 @@ static inline bool regime_is_gcs(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, GCS); } +/* Return the GCS MMUIdx for a given regime. */ +static inline ARMMMUIdx regime_to_gcs(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + uint32_t core = FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, TG); + tcg_debug_assert(core != 0); /* core 0 is E10_0, not a GCS index */ + return core | ARM_MMU_IDX_A; +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 42b003db9c..a4663c8d87 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -16,27 +16,29 @@ #define S1 R_MMUIDXINFO_STAGE1_MASK #define S2 R_MMUIDXINFO_STAGE2_MASK #define GCS R_MMUIDXINFO_GCS_MASK +#define TG(X) \ + ((ARMMMUIdx_##X##_GCS & ARM_MMU_IDX_COREIDX_MASK) << R_MMUIDXINFO_TG_SHIFT) const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] = { /* * A-profile. */ - [ARMMMUIdx_E10_0] = EL(0) | REL(1) | R2, + [ARMMMUIdx_E10_0] = EL(0) | REL(1) | R2 | TG(E10_0), [ARMMMUIdx_E10_0_GCS] = EL(0) | REL(1) | R2 | GCS, - [ARMMMUIdx_E10_1] = EL(1) | REL(1) | R2, - [ARMMMUIdx_E10_1_PAN] = EL(1) | REL(1) | R2 | PAN, + [ARMMMUIdx_E10_1] = EL(1) | REL(1) | R2 | TG(E10_1), + [ARMMMUIdx_E10_1_PAN] = EL(1) | REL(1) | R2 | TG(E10_1) | PAN, [ARMMMUIdx_E10_1_GCS] = EL(1) | REL(1) | R2 | GCS, - [ARMMMUIdx_E20_0] = EL(0) | REL(2) | R2, + [ARMMMUIdx_E20_0] = EL(0) | REL(2) | R2 | TG(E20_0), [ARMMMUIdx_E20_0_GCS] = EL(0) | REL(2) | R2 | GCS, - [ARMMMUIdx_E20_2] = EL(2) | REL(2) | R2, - [ARMMMUIdx_E20_2_PAN] = EL(2) | REL(2) | R2 | PAN, + [ARMMMUIdx_E20_2] = EL(2) | REL(2) | R2 | TG(E20_2), + [ARMMMUIdx_E20_2_PAN] = EL(2) | REL(2) | R2 | TG(E20_2) | PAN, [ARMMMUIdx_E20_2_GCS] = EL(2) | REL(2) | R2 | GCS, - [ARMMMUIdx_E2] = EL(2) | REL(2), + [ARMMMUIdx_E2] = EL(2) | REL(2) | TG(E2), [ARMMMUIdx_E2_GCS] = EL(2) | REL(2) | GCS, - [ARMMMUIdx_E3] = EL(3) | REL(3), + [ARMMMUIdx_E3] = EL(3) | REL(3) | TG(E3), [ARMMMUIdx_E3_GCS] = EL(3) | REL(3) | GCS, [ARMMMUIdx_E30_0] = EL(0) | REL(3), [ARMMMUIdx_E30_3_PAN] = EL(3) | REL(3) | PAN, @@ -44,10 +46,10 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] = { [ARMMMUIdx_Stage2_S] = REL(2) | S2, [ARMMMUIdx_Stage2] = REL(2) | S2, - [ARMMMUIdx_Stage1_E0] = REL(1) | R2 | S1 | USER, + [ARMMMUIdx_Stage1_E0] = REL(1) | R2 | S1 | USER | TG(Stage1_E0), [ARMMMUIdx_Stage1_E0_GCS] = REL(1) | R2 | S1 | USER | GCS, - [ARMMMUIdx_Stage1_E1] = REL(1) | R2 | S1, - [ARMMMUIdx_Stage1_E1_PAN] = REL(1) | R2 | S1 | PAN, + [ARMMMUIdx_Stage1_E1] = REL(1) | R2 | S1 | TG(Stage1_E1), + [ARMMMUIdx_Stage1_E1_PAN] = REL(1) | R2 | S1 | TG(Stage1_E1) | PAN, [ARMMMUIdx_Stage1_E1_GCS] = REL(1) | R2 | S1 | GCS, /*