From: liuhongt <hongtao.liu@intel.com>
Date: Mon, 24 Aug 2020 12:52:20 +0000 (+0800)
Subject: Refine typo to fix ICE.
X-Git-Tag: basepoints/gcc-12~5424
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=108477875f01798eecd7780207396b8c44930ae9;p=thirdparty%2Fgcc.git

Refine typo to fix ICE.

2020-08-24  Hongtao Liu  <hongtao.liu@intel.com>

gcc/ChangeLog:
	PR target/96755
	* config/i386/sse.md: Correct the mode of NOT operands to
	SImode.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr96755.c: New test.
---

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6f1f7f79673b..380dc453b0d8 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1588,7 +1588,7 @@
 (define_split
   [(set (match_operand:DI 0 "mask_reg_operand")
 	(zero_extend:DI
-	  (not:DI (match_operand:SI 1 "mask_reg_operand"))))]
+	  (not:SI (match_operand:SI 1 "mask_reg_operand"))))]
   "TARGET_AVX512BW && reload_completed"
   [(parallel
      [(set (match_dup 0)
diff --git a/gcc/testsuite/gcc.target/i386/pr96755.c b/gcc/testsuite/gcc.target/i386/pr96755.c
new file mode 100644
index 000000000000..20fed5899982
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr96755.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=skylake-avx512" } */
+
+extern long var_22;
+extern int arr_3[];
+extern int arr_4[][20][9];
+short a;
+void test(unsigned short b, unsigned char e, long long g) {
+  for (long c = 0; c < 20ULL; c = g)
+    for (short d = 0; d < 9; d++)
+      for (char f = e; f < 8; f += 4) {
+        arr_3[f] = 0;
+        var_22 = ~(unsigned)b;
+        arr_4[c][d][f] = a;
+      }
+}