From: Arnd Bergmann Date: Wed, 23 Jul 2025 20:10:11 +0000 (+0200) Subject: Merge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/dt X-Git-Tag: v6.17-rc1~172^2~4 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=11949d263a565d7ec277729b5e6c1a4fed51d901;p=thirdparty%2Fkernel%2Flinux.git Merge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/dt RISC-V Devicetrees for v6.17 Sophgo: For CV18xx serials: There are three major changes. The first is to add the RTCSYS MFD node, which provides rich control registers for soc power management and other rich control functions; the second is to add the reset controller node and add related reset properties for other peripherals; the third is to add ethernet controller related nodes to the soc and enable ethernet device control for HuashanPi. For SG2042: There are three major changes. The first is to add ISA extensions such as xtheadvector/ziccrse/zfh for cpu cores; the second is add ethernet controller support; the third is add two new boards EVB_V1 & EVB_V2 which use SG2042 SoC. For SG2044: There are many changes. The first is to add pmu configuration; the second is to add ISA extensions ziccrse and add missing riscv,cbop-block-size property for cpu cores; the third is to add more peripherals nodes for SoC after clock controller is ready, such as MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU device for the sophgo-srd3-10 board and reserve uart0 node for sophgo-srd3-10 board because uart0 is already occupied by the firmware. This PR also moves sophgo.yaml from the riscv directory to soc/sophgo for sharing between riscv and arm. CV18xx SoC contains a RISC-V big core and an ARM64 big core. Moving sophgo.yaml to a shared location will help us add support for ARM cores to the CV18xx chip in the future. Signed-off-by: Chen Wang * tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: (32 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ... Link: https://lore.kernel.org/r/MAUPR01MB1107297124C9DA0CD77DA3DC1FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann --- 11949d263a565d7ec277729b5e6c1a4fed51d901