From: Russell King (Oracle) Date: Mon, 10 Nov 2025 14:42:43 +0000 (+0000) Subject: net: stmmac: meson8b: use PHY_INTF_SEL_x X-Git-Tag: v6.19-rc1~170^2~187^2~2 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=12f42597ab148753959bc466c0c66abcf10e4267;p=thirdparty%2Fkernel%2Flinux.git net: stmmac: meson8b: use PHY_INTF_SEL_x Use PHY_INTF_SEL_x definitions for phy_intf_sel bitfield. Reviewed-by: Martin Blumenstingl Signed-off-by: Russell King (Oracle) Link: https://patch.msgid.link/E1vIT6R-0000000DpPL-0Nli@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski --- diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index a50782994b979..f485b9b858bf6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -26,8 +26,8 @@ #define PRG_ETH0_RGMII_MODE BIT(0) #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) -#define PRG_ETH0_EXT_RGMII_MODE 1 -#define PRG_ETH0_EXT_RMII_MODE 4 +#define PRG_ETH0_EXT_RGMII_MODE PHY_INTF_SEL_RGMII +#define PRG_ETH0_EXT_RMII_MODE PHY_INTF_SEL_RMII /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)