From: Kaz Kojima Date: Tue, 23 Mar 2010 23:07:42 +0000 (+0000) Subject: backport: sh.c (sh_expand_epilogue): Fix interrupt handler register popping order. X-Git-Tag: releases/gcc-4.3.5~127 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1311ed9d1fc98842e0da7c4b15160585f02fcc03;p=thirdparty%2Fgcc.git backport: sh.c (sh_expand_epilogue): Fix interrupt handler register popping order. Backport from mainline: 2010-01-08 DJ Delorie * config/sh/sh.c (sh_expand_epilogue): Fix interrupt handler register popping order. From-SVN: r157684 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 92e531f886b6..3b6692cc69ba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2010-03-23 Kaz Kojima + + Backport from mainline: + 2010-01-08 DJ Delorie + + * config/sh/sh.c (sh_expand_epilogue): Fix interrupt handler + register popping order. + 2010-03-21 John David Anglin PR middle-end/42718 diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 2db614209a40..7748153343e5 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -1,6 +1,6 @@ /* Output routines for GCC for Renesas / SuperH SH. Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. + 2003, 2004, 2005, 2006, 2007, 2008, 2010 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com). @@ -6720,13 +6720,13 @@ sh_expand_epilogue (bool sibcall_p) pop (PR_REG); } - /* Banked registers are poped first to avoid being scheduled in the + /* Banked registers are popped first to avoid being scheduled in the delay slot. RTE switches banks before the ds instruction. */ if (current_function_interrupt) { - for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) - if (TEST_HARD_REG_BIT (live_regs_mask, i)) - pop (LAST_BANKED_REG - i); + for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--) + if (TEST_HARD_REG_BIT (live_regs_mask, i)) + pop (i); last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1; }