From: Andy Yan Date: Sun, 15 Jun 2025 12:39:05 +0000 (+0800) Subject: clk: rockchip: rk3568: Add PLL rate for 132MHz X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=132b62280a9dbe38c627183ae7f1611de3ee0d9a;p=thirdparty%2Fkernel%2Flinux.git clk: rockchip: rk3568: Add PLL rate for 132MHz Add PLL rate for 132 MHz to allow raydium-rm67200 panel with 1080x1920 resolution to run at 60 fps that driven by VPLL. Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20250615123922.661998-1-andyshrk@163.com Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index d48ab9d6c0646..97d279399ae84 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), + RK3036_PLL_RATE(132000000, 1, 66, 6, 2, 1, 0), RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0), RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0), RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),