From: Juzhe-Zhong Date: Sun, 4 Jun 2023 09:36:47 +0000 (+0800) Subject: RISC-V: Move optimization patterns into autovec-opt.md X-Git-Tag: basepoints/gcc-15~8610 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1330977166aa8b3035b6314f5d3bac362f77be6b;p=thirdparty%2Fgcc.git RISC-V: Move optimization patterns into autovec-opt.md Move all optimization patterns into autovec-opt.md to make organization easier maintain. gcc/ChangeLog: * config/riscv/autovec-opt.md (*not): Move to autovec-opt.md. (*n): Ditto. * config/riscv/autovec.md (*not): Ditto. (*n): Ditto. * config/riscv/vector.md: Ditto. --- diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 92cdc4e9a167..f6052b505728 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -78,3 +78,95 @@ "vwmulsu.vv\t%0,%3,%4%p1" [(set_attr "type" "viwmul") (set_attr "mode" "")]) + +;; ----------------------------------------------------------------------------- +;; ---- Integer Compare Instructions Simplification +;; ----------------------------------------------------------------------------- +;; Simplify OP(V, V) Instructions to VMCLR.m Includes: +;; - 1. VMSNE +;; - 2. VMSLT +;; - 3. VMSLTU +;; - 4. VMSGT +;; - 5. VMSGTU +;; ----------------------------------------------------------------------------- +;; Simplify OP(V, V) Instructions to VMSET.m Includes: +;; - 1. VMSEQ +;; - 2. VMSLE +;; - 3. VMSLEU +;; - 4. VMSGE +;; - 5. VMSGEU +;; ----------------------------------------------------------------------------- + +(define_split + [(set (match_operand:VB 0 "register_operand") + (if_then_else:VB + (unspec:VB + [(match_operand:VB 1 "vector_all_trues_mask_operand") + (match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:VB 3 "vector_move_operand") + (match_operand:VB 2 "vector_undef_operand")))] + "TARGET_VECTOR" + [(const_int 0)] + { + emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (mode), + RVV_VUNDEF (mode), operands[3], + operands[4], operands[5])); + DONE; + } +) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations (inverted second input) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmandnot.mm +;; - vmornot.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "*not" + [(set (match_operand:VB 0 "register_operand" "=vr") + (bitmanip_bitwise:VB + (not:VB (match_operand:VB 2 "register_operand" " vr")) + (match_operand:VB 1 "register_operand" " vr")))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_not (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [BOOL] Binary logical operations (inverted result) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmnand.mm +;; - vmnor.mm +;; - vmxnor.mm +;; ------------------------------------------------------------------------- + +(define_insn_and_split "*n" + [(set (match_operand:VB 0 "register_operand" "=vr") + (not:VB + (any_bitwise:VB + (match_operand:VB 1 "register_operand" " vr") + (match_operand:VB 2 "register_operand" " vr"))))] + "TARGET_VECTOR" + "#" + "&& can_create_pseudo_p ()" + [(const_int 0)] + { + insn_code icode = code_for_pred_n (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); + DONE; + } + [(set_attr "type" "vmalu") + (set_attr "mode" "")]) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 5c3aad7ee44f..4fe0e3253dc2 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -228,58 +228,6 @@ [(set_attr "type" "vmalu") (set_attr "mode" "")]) -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted second input) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmandnot.mm -;; - vmornot.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*not" - [(set (match_operand:VB 0 "register_operand" "=vr") - (bitmanip_bitwise:VB - (not:VB (match_operand:VB 2 "register_operand" " vr")) - (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" - "#" - "&& can_create_pseudo_p ()" - [(const_int 0)] - { - insn_code icode = code_for_pred_not (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "")]) - -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted result) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmnand.mm -;; - vmnor.mm -;; - vmxnor.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*n" - [(set (match_operand:VB 0 "register_operand" "=vr") - (not:VB - (any_bitwise:VB - (match_operand:VB 1 "register_operand" " vr") - (match_operand:VB 2 "register_operand" " vr"))))] - "TARGET_VECTOR" - "#" - "&& can_create_pseudo_p ()" - [(const_int 0)] - { - insn_code icode = code_for_pred_n (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "")]) - ;; ========================================================================= ;; == Comparisons and selects ;; ========================================================================= diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 79f1644732aa..055ad35fde54 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -8417,44 +8417,5 @@ [(set_attr "type" "vssegtx") (set_attr "mode" "")]) -;; ----------------------------------------------------------------------------- -;; ---- Integer Compare Instructions Simplification -;; ----------------------------------------------------------------------------- -;; Simplify OP(V, V) Instructions to VMCLR.m Includes: -;; - 1. VMSNE -;; - 2. VMSLT -;; - 3. VMSLTU -;; - 4. VMSGT -;; - 5. VMSGTU -;; ----------------------------------------------------------------------------- -;; Simplify OP(V, V) Instructions to VMSET.m Includes: -;; - 1. VMSEQ -;; - 2. VMSLE -;; - 3. VMSLEU -;; - 4. VMSGE -;; - 5. VMSGEU -;; ----------------------------------------------------------------------------- -(define_split - [(set (match_operand:VB 0 "register_operand") - (if_then_else:VB - (unspec:VB - [(match_operand:VB 1 "vector_all_trues_mask_operand") - (match_operand 4 "vector_length_operand") - (match_operand 5 "const_int_operand") - (match_operand 6 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VB 3 "vector_move_operand") - (match_operand:VB 2 "vector_undef_operand")))] - "TARGET_VECTOR" - [(const_int 0)] - { - emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (mode), - RVV_VUNDEF (mode), operands[3], - operands[4], operands[5])); - DONE; - } -) - (include "autovec.md") (include "autovec-opt.md")