From: David Lechner Date: Fri, 6 Mar 2026 22:05:55 +0000 (-0600) Subject: clk: mediatek: set CLK_PARENT_XTAL on fixed factor clocks X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=142c805d470cd02470146d6d70aa9c522d4da16c;p=thirdparty%2Fu-boot.git clk: mediatek: set CLK_PARENT_XTAL on fixed factor clocks Explicitly set the CLK_PARENT_XTAL flag for fixed factor clocks. Prior to this, it was assumed that clock ID 0 was CLK_XTAL and other IDs used a different clock tree when no parent was explicitly set. Making the parent explicit will allow us to remove this confusing behavior in the future. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-8-b253b49f17b2@baylibre.com Signed-off-by: David Lechner --- diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 077820550a5..44d2836710e 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -95,7 +95,7 @@ static const struct mtk_gate apmixed_cgs[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 4d16610f4d0..d52555283d2 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -269,7 +269,7 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_DPI, 108 * MHZ), diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 85011f5327b..1d697539ce2 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -71,7 +71,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index 69576304f2f..7af5858286c 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -69,7 +69,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index dac4aad61ef..9d03e245886 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -62,7 +62,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index c19828def06..e7de9d33e00 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -64,7 +64,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000),