From: Biju Das Date: Wed, 15 Jan 2025 10:38:53 +0000 (+0000) Subject: arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes X-Git-Tag: v6.15-rc1~159^2~35^2~26 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=146a9b058ec780581f580b0de9bbc0264b59d701;p=thirdparty%2Fkernel%2Fstable.git arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes Add WDT1-WDT3 nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250115103858.104709-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 200e9ea891935..133aa3272d3a7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -175,6 +175,36 @@ status = "disabled"; }; + wdt1: watchdog@14400000 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x14400000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x76>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@13000000 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x13000000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x77>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@13000400 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x13000400 0 0x400>; + clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x78>; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>;