From: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Date: Tue, 27 May 2014 16:09:54 +0000 (+0100)
Subject: target-arm: A64: Trap ERET from EL0 at translation time
X-Git-Tag: v2.1.0-rc0~99^2~5
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=14c521d45eb08b2a829b0fa90c682a7f0664ee85;p=thirdparty%2Fqemu.git

target-arm: A64: Trap ERET from EL0 at translation time

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1400980132-25949-19-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index bfd139afe54..ec6a39d1d60 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1507,6 +1507,10 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
         tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
         break;
     case 4: /* ERET */
+        if (s->current_pl == 0) {
+            unallocated_encoding(s);
+            return;
+        }
         gen_helper_exception_return(cpu_env);
         s->is_jmp = DISAS_JUMP;
         return;