From: Greg Kroah-Hartman Date: Mon, 8 Jan 2024 12:48:42 +0000 (+0100) Subject: 6.1-stable patches X-Git-Tag: v4.14.336~11 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=14ed80ca9598d3c5cc2f4c8d7c29a456b81ff6e9;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: drm-amd-display-add-nv12-bounding-box.patch drm-amdgpu-skip-gpu_info-fw-loading-on-navi12.patch mmc-core-cancel-delayed-work-before-releasing-host.patch mmc-meson-mx-sdhc-fix-initialization-frozen-issue.patch mmc-rpmb-fixes-pause-retune-on-all-rpmb-partitions.patch mmc-sdhci-sprd-fix-emmc-init-failure-after-hw-reset.patch --- diff --git a/queue-6.1/drm-amd-display-add-nv12-bounding-box.patch b/queue-6.1/drm-amd-display-add-nv12-bounding-box.patch new file mode 100644 index 00000000000..e4a5a2e3d59 --- /dev/null +++ b/queue-6.1/drm-amd-display-add-nv12-bounding-box.patch @@ -0,0 +1,140 @@ +From 7e725c20fea8914ef1829da777f517ce1a93d388 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 20 Dec 2023 12:33:45 -0500 +Subject: drm/amd/display: add nv12 bounding box + +From: Alex Deucher + +commit 7e725c20fea8914ef1829da777f517ce1a93d388 upstream. + +This was included in gpu_info firmware, move it into the +driver for consistency with other nv1x parts. + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2318 +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 110 ++++++++++++++++++- + 1 file changed, 109 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +@@ -438,7 +438,115 @@ struct _vcs_dpi_soc_bounding_box_st dcn2 + .use_urgent_burst_bw = 0 + }; + +-struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; ++struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { ++ .clock_limits = { ++ { ++ .state = 0, ++ .dcfclk_mhz = 560.0, ++ .fabricclk_mhz = 560.0, ++ .dispclk_mhz = 513.0, ++ .dppclk_mhz = 513.0, ++ .phyclk_mhz = 540.0, ++ .socclk_mhz = 560.0, ++ .dscclk_mhz = 171.0, ++ .dram_speed_mts = 1069.0, ++ }, ++ { ++ .state = 1, ++ .dcfclk_mhz = 694.0, ++ .fabricclk_mhz = 694.0, ++ .dispclk_mhz = 642.0, ++ .dppclk_mhz = 642.0, ++ .phyclk_mhz = 600.0, ++ .socclk_mhz = 694.0, ++ .dscclk_mhz = 214.0, ++ .dram_speed_mts = 1324.0, ++ }, ++ { ++ .state = 2, ++ .dcfclk_mhz = 875.0, ++ .fabricclk_mhz = 875.0, ++ .dispclk_mhz = 734.0, ++ .dppclk_mhz = 734.0, ++ .phyclk_mhz = 810.0, ++ .socclk_mhz = 875.0, ++ .dscclk_mhz = 245.0, ++ .dram_speed_mts = 1670.0, ++ }, ++ { ++ .state = 3, ++ .dcfclk_mhz = 1000.0, ++ .fabricclk_mhz = 1000.0, ++ .dispclk_mhz = 1100.0, ++ .dppclk_mhz = 1100.0, ++ .phyclk_mhz = 810.0, ++ .socclk_mhz = 1000.0, ++ .dscclk_mhz = 367.0, ++ .dram_speed_mts = 2000.0, ++ }, ++ { ++ .state = 4, ++ .dcfclk_mhz = 1200.0, ++ .fabricclk_mhz = 1200.0, ++ .dispclk_mhz = 1284.0, ++ .dppclk_mhz = 1284.0, ++ .phyclk_mhz = 810.0, ++ .socclk_mhz = 1200.0, ++ .dscclk_mhz = 428.0, ++ .dram_speed_mts = 2000.0, ++ }, ++ { ++ .state = 5, ++ .dcfclk_mhz = 1200.0, ++ .fabricclk_mhz = 1200.0, ++ .dispclk_mhz = 1284.0, ++ .dppclk_mhz = 1284.0, ++ .phyclk_mhz = 810.0, ++ .socclk_mhz = 1200.0, ++ .dscclk_mhz = 428.0, ++ .dram_speed_mts = 2000.0, ++ }, ++ }, ++ ++ .num_states = 5, ++ .sr_exit_time_us = 1.9, ++ .sr_enter_plus_exit_time_us = 4.4, ++ .urgent_latency_us = 3.0, ++ .urgent_latency_pixel_data_only_us = 4.0, ++ .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, ++ .urgent_latency_vm_data_only_us = 4.0, ++ .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, ++ .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, ++ .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, ++ .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, ++ .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, ++ .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, ++ .max_avg_sdp_bw_use_normal_percent = 40.0, ++ .max_avg_dram_bw_use_normal_percent = 40.0, ++ .writeback_latency_us = 12.0, ++ .ideal_dram_bw_after_urgent_percent = 40.0, ++ .max_request_size_bytes = 256, ++ .dram_channel_width_bytes = 16, ++ .fabric_datapath_to_dcn_data_return_bytes = 64, ++ .dcn_downspread_percent = 0.5, ++ .downspread_percent = 0.5, ++ .dram_page_open_time_ns = 50.0, ++ .dram_rw_turnaround_time_ns = 17.5, ++ .dram_return_buffer_per_channel_bytes = 8192, ++ .round_trip_ping_latency_dcfclk_cycles = 131, ++ .urgent_out_of_order_return_per_channel_bytes = 4096, ++ .channel_interleave_bytes = 256, ++ .num_banks = 8, ++ .num_chans = 16, ++ .vmm_page_size_bytes = 4096, ++ .dram_clock_change_latency_us = 45.0, ++ .writeback_dram_clock_change_latency_us = 23.0, ++ .return_bus_width_bytes = 64, ++ .dispclk_dppclk_vco_speed_mhz = 3850, ++ .xfc_bus_transport_time_us = 20, ++ .xfc_xbuf_latency_tolerance_us = 50, ++ .use_urgent_burst_bw = 0, ++}; + + struct _vcs_dpi_ip_params_st dcn2_1_ip = { + .odm_capable = 1, diff --git a/queue-6.1/drm-amdgpu-skip-gpu_info-fw-loading-on-navi12.patch b/queue-6.1/drm-amdgpu-skip-gpu_info-fw-loading-on-navi12.patch new file mode 100644 index 00000000000..8019d7de209 --- /dev/null +++ b/queue-6.1/drm-amdgpu-skip-gpu_info-fw-loading-on-navi12.patch @@ -0,0 +1,40 @@ +From 21f6137c64c65d6808c4a81006956197ca203383 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 20 Dec 2023 12:36:08 -0500 +Subject: drm/amdgpu: skip gpu_info fw loading on navi12 + +From: Alex Deucher + +commit 21f6137c64c65d6808c4a81006956197ca203383 upstream. + +It's no longer required. + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2318 +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 ++--------- + 1 file changed, 2 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1976,15 +1976,8 @@ static int amdgpu_device_parse_gpu_info_ + + adev->firmware.gpu_info_fw = NULL; + +- if (adev->mman.discovery_bin) { +- /* +- * FIXME: The bounding box is still needed by Navi12, so +- * temporarily read it from gpu_info firmware. Should be dropped +- * when DAL no longer needs it. +- */ +- if (adev->asic_type != CHIP_NAVI12) +- return 0; +- } ++ if (adev->mman.discovery_bin) ++ return 0; + + switch (adev->asic_type) { + default: diff --git a/queue-6.1/mmc-core-cancel-delayed-work-before-releasing-host.patch b/queue-6.1/mmc-core-cancel-delayed-work-before-releasing-host.patch new file mode 100644 index 00000000000..f679445b81b --- /dev/null +++ b/queue-6.1/mmc-core-cancel-delayed-work-before-releasing-host.patch @@ -0,0 +1,96 @@ +From 1036f69e251380573e256568cf814506e3fb9988 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 4 Dec 2023 12:29:53 +0100 +Subject: mmc: core: Cancel delayed work before releasing host + +From: Geert Uytterhoeven + +commit 1036f69e251380573e256568cf814506e3fb9988 upstream. + +On RZ/Five SMARC EVK, where probing of SDHI is deferred due to probe +deferral of the vqmmc-supply regulator: + + ------------[ cut here ]------------ + WARNING: CPU: 0 PID: 0 at kernel/time/timer.c:1738 __run_timers.part.0+0x1d0/0x1e8 + Modules linked in: + CPU: 0 PID: 0 Comm: swapper Not tainted 6.7.0-rc4 #101 + Hardware name: Renesas SMARC EVK based on r9a07g043f01 (DT) + epc : __run_timers.part.0+0x1d0/0x1e8 + ra : __run_timers.part.0+0x134/0x1e8 + epc : ffffffff800771a4 ra : ffffffff80077108 sp : ffffffc800003e60 + gp : ffffffff814f5028 tp : ffffffff8140c5c0 t0 : ffffffc800000000 + t1 : 0000000000000001 t2 : ffffffff81201300 s0 : ffffffc800003f20 + s1 : ffffffd8023bc4a0 a0 : 00000000fffee6b0 a1 : 0004010000400000 + a2 : ffffffffc0000016 a3 : ffffffff81488640 a4 : ffffffc800003e60 + a5 : 0000000000000000 a6 : 0000000004000000 a7 : ffffffc800003e68 + s2 : 0000000000000122 s3 : 0000000000200000 s4 : 0000000000000000 + s5 : ffffffffffffffff s6 : ffffffff81488678 s7 : ffffffff814886c0 + s8 : ffffffff814f49c0 s9 : ffffffff81488640 s10: 0000000000000000 + s11: ffffffc800003e60 t3 : 0000000000000240 t4 : 0000000000000a52 + t5 : ffffffd8024ae018 t6 : ffffffd8024ae038 + status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003 + [] __run_timers.part.0+0x1d0/0x1e8 + [] run_timer_softirq+0x24/0x4a + [] __do_softirq+0xc6/0x1fa + [] irq_exit_rcu+0x66/0x84 + [] handle_riscv_irq+0x40/0x4e + [] call_on_irq_stack+0x1c/0x28 + ---[ end trace 0000000000000000 ]--- + +What happens? + + renesas_sdhi_probe() + { + tmio_mmc_host_alloc() + mmc_alloc_host() + INIT_DELAYED_WORK(&host->detect, mmc_rescan); + + devm_request_irq(tmio_mmc_irq); + + /* + * After this, the interrupt handler may be invoked at any time + * + * tmio_mmc_irq() + * { + * __tmio_mmc_card_detect_irq() + * mmc_detect_change() + * _mmc_detect_change() + * mmc_schedule_delayed_work(&host->detect, delay); + * } + */ + + tmio_mmc_host_probe() + tmio_mmc_init_ocr() + -EPROBE_DEFER + + tmio_mmc_host_free() + mmc_free_host() + } + +When expire_timers() runs later, it warns because the MMC host structure +containing the delayed work was freed, and now contains an invalid work +function pointer. + +Fix this by cancelling any pending delayed work before releasing the +MMC host structure. + +Signed-off-by: Geert Uytterhoeven +Tested-by: Lad Prabhakar +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/205dc4c91b47e31b64392fe2498c7a449e717b4b.1701689330.git.geert+renesas@glider.be +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mmc/core/host.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mmc/core/host.c ++++ b/drivers/mmc/core/host.c +@@ -670,6 +670,7 @@ EXPORT_SYMBOL(mmc_remove_host); + */ + void mmc_free_host(struct mmc_host *host) + { ++ cancel_delayed_work_sync(&host->detect); + mmc_pwrseq_free(host); + put_device(&host->class_dev); + } diff --git a/queue-6.1/mmc-meson-mx-sdhc-fix-initialization-frozen-issue.patch b/queue-6.1/mmc-meson-mx-sdhc-fix-initialization-frozen-issue.patch new file mode 100644 index 00000000000..94aa840368f --- /dev/null +++ b/queue-6.1/mmc-meson-mx-sdhc-fix-initialization-frozen-issue.patch @@ -0,0 +1,77 @@ +From 8c124d998ea0c9022e247b11ac51f86ec8afa0e1 Mon Sep 17 00:00:00 2001 +From: Ziyang Huang +Date: Wed, 11 Oct 2023 00:44:00 +0800 +Subject: mmc: meson-mx-sdhc: Fix initialization frozen issue + +From: Ziyang Huang + +commit 8c124d998ea0c9022e247b11ac51f86ec8afa0e1 upstream. + +Commit 4bc31edebde5 ("mmc: core: Set HS clock speed before sending +HS CMD13") set HS clock (52MHz) before switching to HS mode. For this +freq, FCLK_DIV5 will be selected and div value is 10 (reg value is 9). +Then we set rx_clk_phase to 11 or 15 which is out of range and make +hardware frozen. After we send command request, no irq will be +interrupted and the mmc driver will keep to wait for request finished, +even durning rebooting. + +So let's set it to Phase 90 which should work in most cases. Then let +meson_mx_sdhc_execute_tuning() to find the accurate value for data +transfer. + +If this doesn't work, maybe need to define a factor in dts. + +Fixes: e4bf1b0970ef ("mmc: host: meson-mx-sdhc: new driver for the Amlogic Meson SDHC host") +Signed-off-by: Ziyang Huang +Tested-by: Anand Moon +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/TYZPR01MB5556A3E71554A2EC08597EA4C9CDA@TYZPR01MB5556.apcprd01.prod.exchangelabs.com +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mmc/host/meson-mx-sdhc-mmc.c | 26 +++++--------------------- + 1 file changed, 5 insertions(+), 21 deletions(-) + +--- a/drivers/mmc/host/meson-mx-sdhc-mmc.c ++++ b/drivers/mmc/host/meson-mx-sdhc-mmc.c +@@ -269,7 +269,7 @@ static int meson_mx_sdhc_enable_clks(str + static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios) + { + struct meson_mx_sdhc_host *host = mmc_priv(mmc); +- u32 rx_clk_phase; ++ u32 val, rx_clk_phase; + int ret; + + meson_mx_sdhc_disable_clks(mmc); +@@ -290,27 +290,11 @@ static int meson_mx_sdhc_set_clk(struct + mmc->actual_clock = clk_get_rate(host->sd_clk); + + /* +- * according to Amlogic the following latching points are +- * selected with empirical values, there is no (known) formula +- * to calculate these. ++ * Phase 90 should work in most cases. For data transmission, ++ * meson_mx_sdhc_execute_tuning() will find a accurate value + */ +- if (mmc->actual_clock > 100000000) { +- rx_clk_phase = 1; +- } else if (mmc->actual_clock > 45000000) { +- if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) +- rx_clk_phase = 15; +- else +- rx_clk_phase = 11; +- } else if (mmc->actual_clock >= 25000000) { +- rx_clk_phase = 15; +- } else if (mmc->actual_clock > 5000000) { +- rx_clk_phase = 23; +- } else if (mmc->actual_clock > 1000000) { +- rx_clk_phase = 55; +- } else { +- rx_clk_phase = 1061; +- } +- ++ regmap_read(host->regmap, MESON_SDHC_CLKC, &val); ++ rx_clk_phase = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val) / 4; + regmap_update_bits(host->regmap, MESON_SDHC_CLK2, + MESON_SDHC_CLK2_RX_CLK_PHASE, + FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE, diff --git a/queue-6.1/mmc-rpmb-fixes-pause-retune-on-all-rpmb-partitions.patch b/queue-6.1/mmc-rpmb-fixes-pause-retune-on-all-rpmb-partitions.patch new file mode 100644 index 00000000000..470e91bf1d2 --- /dev/null +++ b/queue-6.1/mmc-rpmb-fixes-pause-retune-on-all-rpmb-partitions.patch @@ -0,0 +1,60 @@ +From e7794c14fd73e5eb4a3e0ecaa5334d5a17377c50 Mon Sep 17 00:00:00 2001 +From: Jorge Ramirez-Ortiz +Date: Fri, 1 Dec 2023 16:31:43 +0100 +Subject: mmc: rpmb: fixes pause retune on all RPMB partitions. + +From: Jorge Ramirez-Ortiz + +commit e7794c14fd73e5eb4a3e0ecaa5334d5a17377c50 upstream. + +When RPMB was converted to a character device, it added support for +multiple RPMB partitions (Commit 97548575bef3 ("mmc: block: Convert RPMB to +a character device"). + +One of the changes in this commit was transforming the variable target_part +defined in __mmc_blk_ioctl_cmd into a bitmask. This inadvertently regressed +the validation check done in mmc_blk_part_switch_pre() and +mmc_blk_part_switch_post(), so let's fix it. + +Fixes: 97548575bef3 ("mmc: block: Convert RPMB to a character device") +Signed-off-by: Jorge Ramirez-Ortiz +Reviewed-by: Linus Walleij +Cc: +Link: https://lore.kernel.org/r/20231201153143.1449753-1-jorge@foundries.io +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mmc/core/block.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/mmc/core/block.c ++++ b/drivers/mmc/core/block.c +@@ -866,9 +866,10 @@ static const struct block_device_operati + static int mmc_blk_part_switch_pre(struct mmc_card *card, + unsigned int part_type) + { ++ const unsigned int mask = EXT_CSD_PART_CONFIG_ACC_RPMB; + int ret = 0; + +- if (part_type == EXT_CSD_PART_CONFIG_ACC_RPMB) { ++ if ((part_type & mask) == mask) { + if (card->ext_csd.cmdq_en) { + ret = mmc_cmdq_disable(card); + if (ret) +@@ -883,9 +884,10 @@ static int mmc_blk_part_switch_pre(struc + static int mmc_blk_part_switch_post(struct mmc_card *card, + unsigned int part_type) + { ++ const unsigned int mask = EXT_CSD_PART_CONFIG_ACC_RPMB; + int ret = 0; + +- if (part_type == EXT_CSD_PART_CONFIG_ACC_RPMB) { ++ if ((part_type & mask) == mask) { + mmc_retune_unpause(card->host); + if (card->reenable_cmdq && !card->ext_csd.cmdq_en) + ret = mmc_cmdq_enable(card); +@@ -3180,4 +3182,3 @@ module_exit(mmc_blk_exit); + + MODULE_LICENSE("GPL"); + MODULE_DESCRIPTION("Multimedia Card (MMC) block device driver"); +- diff --git a/queue-6.1/mmc-sdhci-sprd-fix-emmc-init-failure-after-hw-reset.patch b/queue-6.1/mmc-sdhci-sprd-fix-emmc-init-failure-after-hw-reset.patch new file mode 100644 index 00000000000..34d22fe423c --- /dev/null +++ b/queue-6.1/mmc-sdhci-sprd-fix-emmc-init-failure-after-hw-reset.patch @@ -0,0 +1,48 @@ +From 8abf77c88929b6d20fa4f9928b18d6448d64e293 Mon Sep 17 00:00:00 2001 +From: Wenchao Chen +Date: Mon, 4 Dec 2023 14:49:34 +0800 +Subject: mmc: sdhci-sprd: Fix eMMC init failure after hw reset + +From: Wenchao Chen + +commit 8abf77c88929b6d20fa4f9928b18d6448d64e293 upstream. + +Some eMMC devices that do not close the auto clk gate after hw reset will +cause eMMC initialization to fail. Let's fix this. + +Signed-off-by: Wenchao Chen +Fixes: ff874dbc4f86 ("mmc: sdhci-sprd: Disable CLK_AUTO when the clock is less than 400K") +Reviewed-by: Baolin Wang +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20231204064934.21236-1-wenchao.chen@unisoc.com +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mmc/host/sdhci-sprd.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +--- a/drivers/mmc/host/sdhci-sprd.c ++++ b/drivers/mmc/host/sdhci-sprd.c +@@ -228,15 +228,19 @@ static inline void _sdhci_sprd_set_clock + div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, div); + ++ val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); ++ mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + /* Enable CLK_AUTO when the clock is greater than 400K. */ + if (clk > 400000) { +- val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); +- mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | +- SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } ++ } else { ++ if (val & mask) { ++ val &= ~mask; ++ sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); ++ } + } + } + diff --git a/queue-6.1/series b/queue-6.1/series index 2830ea7500d..fabd28403cb 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -133,3 +133,9 @@ firewire-ohci-suppress-unexpected-system-reboot-in-amd-ryzen-machines-and-asm108 x86-kprobes-fix-incorrect-return-address-calculation-in-kprobe_emulate_call_indirect.patch i2c-core-fix-atomic-xfer-check-for-non-preempt-config.patch mm-fix-unmap_mapping_range-high-bits-shift-bug.patch +drm-amdgpu-skip-gpu_info-fw-loading-on-navi12.patch +drm-amd-display-add-nv12-bounding-box.patch +mmc-meson-mx-sdhc-fix-initialization-frozen-issue.patch +mmc-rpmb-fixes-pause-retune-on-all-rpmb-partitions.patch +mmc-core-cancel-delayed-work-before-releasing-host.patch +mmc-sdhci-sprd-fix-emmc-init-failure-after-hw-reset.patch