From: Jakub Jelinek <jakub@redhat.com>
Date: Sat, 7 Feb 2026 10:08:17 +0000 (+0100)
Subject: Fix comment typos in permutation spelling
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=15ca69befd0e0a5408284a532affe9085742fd86;p=thirdparty%2Fgcc.git

Fix comment typos in permutation spelling

Noticed two weird ways to spell permutation in some comments.

2026-02-07  Jakub Jelinek  <jakub@redhat.com>

	* optabs.cc (expand_vec_perm_const): Comment spelling fix,
	permuation -> permutation.
	* config/arm/arm.cc (arm_evpc_neon_vtbl): Likewise.
	* config/loongarch/loongarch.cc (loongarch_try_expand_lsx_vshuf_const):
	Comment spelling fix, permuatation -> permutation.
	(loongarch_is_elem_duplicate): Likewise.  Comment spelling fix,
	permuation -> permutation.
---

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index a8ab7a4fb82..decbeaad0f7 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -32004,7 +32004,7 @@ arm_evpc_neon_vext (struct expand_vec_perm_d *d)
   return true;
 }
 
-/* The NEON VTBL instruction is a fully variable permuation that's even
+/* The NEON VTBL instruction is a fully variable permutation that's even
    stronger than what we expose via VEC_PERM_EXPR.  What it doesn't do
    is mask the index operand as VEC_PERM_EXPR requires.  Therefore we
    can do slightly better by expanding this as a constant where we don't
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 1f26928e901..2c13a86176d 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -8848,7 +8848,7 @@ loongarch_set_handled_components (sbitmap components)
 }
 
 /* Use the vshuf instruction to implement all 128-bit constant vector
-   permuatation.  */
+   permutation.  */
 
 static bool
 loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d)
@@ -9581,7 +9581,7 @@ loongarch_is_elem_duplicate (struct expand_vec_perm_d *d)
    When GCC wants to performs a vector permutation, it provides two op
    reigster, one target register, and a selector.
    In const vector permutation case, GCC provides selector as a char array
-   that contains original value; in variable vector permuatation
+   that contains original value; in variable vector permutation
    (performs via vec_perm<mode> insn template), it provides a vector register.
    We assume that nelt is the elements numbers inside single vector in current
    256bit vector mode.
@@ -9608,7 +9608,7 @@ loongarch_is_elem_duplicate (struct expand_vec_perm_d *d)
    by single instruction easily.
 
    3.  What LASX permutation instruction does:
-   In short, it just execute two independent 128bit vector permuatation, and
+   In short, it just execute two independent 128bit vector permutation, and
    it's the reason that we need to do the jobs below.  We will explain it.
    op0, op1, target, and selector will be separate into high 128bit and low
    128bit, and do permutation as the description below:
@@ -9638,8 +9638,8 @@ loongarch_is_elem_duplicate (struct expand_vec_perm_d *d)
    c) Use other instructions to process op and put correct result into target.
    */
 
-/* Implementation of constant vector permuatation.  This function identifies
-   recognized pattern of permuation selector argument, and use one or more
+/* Implementation of constant vector permutation.  This function identifies
+   recognized pattern of permutation selector argument, and use one or more
    instruction (s) to finish the permutation job correctly.  For unsupported
    patterns, it will return false.  */
 
diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index c3b51465248..e813cf9b215 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -6732,7 +6732,7 @@ expand_vec_perm_const (machine_mode mode, rtx v0, rtx v1,
     v1 = v0;
   v1 = force_reg (mode, v1);
 
-  /* Otherwise expand as a fully variable permuation.  */
+  /* Otherwise expand as a fully variable permutation.  */
 
   /* The optabs are only defined for selectors with the same width
      as the values being permuted.  */