From: Rob Herring (Arm) Date: Tue, 16 Dec 2025 18:01:37 +0000 (-0600) Subject: arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk" X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=15e3ce53673289624bab4e6a60207af4775f4a38;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk" The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The Thunder2 SoC is missing the core "uartclk". In this case, the Linux driver uses single clock for both clock inputs. Let's assume that's how the h/w is wired and make the DT reflect that. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216180136.2794105-2-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index cc860a80af516..70430cb2b053a 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -401,16 +401,16 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x24000000 0x0 0x1000>; interrupts = <1 21 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk50mhz>, <&refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; }; uaa1: serial@87e025000000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x25000000 0x0 0x1000>; interrupts = <1 22 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk50mhz>, <&refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; }; }; };