From: Florian Krohm Date: Sun, 26 Aug 2012 19:05:06 +0000 (+0000) Subject: s390: Add testcase for the ecag insn. Based on patch by X-Git-Tag: svn/VALGRIND_3_9_0~737 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=16690f1ef5dbf0a787d2fa74f730ad7545992edb;p=thirdparty%2Fvalgrind.git s390: Add testcase for the ecag insn. Based on patch by Divya Vyas (divyvyas@linux.vnet.ibm.com). Update opcode list. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12903 --- diff --git a/NEWS b/NEWS index d8592e966b..93fd27fd88 100644 --- a/NEWS +++ b/NEWS @@ -22,6 +22,7 @@ where XXXXXX is the bug number as listed below. 219156 [380] handle statically linked malloc and/or other malloc libs 254088 [380] Valgrind should know about UD2 instruction +275800 [380] s390x: Add support for the ecag instruction (part 1) 284004 [381] == 301281 289584 [381] Unhandled instruction: 0xF 0x29 0xE5 (MOVAPS) 295808 [381] amd64->IR: 0xF3 0xF 0xBC 0xC0 (TZCNT) diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv index e5bdbd0b85..0c2e6259fd 100644 --- a/docs/internals/s390-opcodes.csv +++ b/docs/internals/s390-opcodes.csv @@ -790,7 +790,7 @@ clrt,"compare logical and trap (32)","not implemented", clgrt,"compare logical and trap (64)","not implemented", clfit,"compare logical and trap (32<16)","not implemented", clgit,"compare logical and trap (64<16)","not implemented", -ecag,"extract cache attribute","not implemented","open bugzilla" +ecag,"extract cache attribute",implemented, lrl,"load relative long (32)",implemented, lgrl,"load relative long (64)",implemented, lgfrl,"load relative long (64<32)",implemented, diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am index 04aaaf875e..24eeca5bc0 100644 --- a/none/tests/s390x/Makefile.am +++ b/none/tests/s390x/Makefile.am @@ -8,7 +8,7 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \ op_exception fgx stck stckf stcke stfle cksm mvcl clcl troo \ trto trot trtt tr tre cij cgij clij clgij crj cgrj clrj clgrj \ cs csg cds cdsg cu21 cu21_1 cu24 cu24_1 cu42 cu12 cu12_1 \ - ex_sig ex_clone cu14 cu14_1 cu41 fpconv + ex_sig ex_clone cu14 cu14_1 cu41 fpconv ecag check_PROGRAMS = $(INSN_TESTS) \ allexec \ diff --git a/none/tests/s390x/ecag.c b/none/tests/s390x/ecag.c new file mode 100644 index 0000000000..31a469f2b6 --- /dev/null +++ b/none/tests/s390x/ecag.c @@ -0,0 +1,73 @@ +#include +#include +#include +#include +#include "opcodes.h" + +uint64_t +ecag(int ai, int li, int ti) +{ + register uint64_t result asm("2") = 0; + register uint64_t input asm("3") = (ai << 4) | (li << 1) | ti; + + asm volatile( ECAG(2,0,3,000,00) + : "=d" (result) : "d" (input)); + return result; +} + +static unsigned +get_level_info(uint64_t topology, unsigned level) +{ + return (topology >> (56 - level * 8)) & 0xff; +} + +int +main(void) +{ + unsigned level; + uint64_t topology; + + topology = ecag(0, 0, 0); // get summary + + /* ECAG supports at most 8 levels of cache. Iterate over all of them + ignoring those not present. */ + for (level = 0; level < 8; level++) { + unsigned info = get_level_info(topology, level); + + if ((info & 0xc) == 0) continue; // cache does not exist at this level + + unsigned cache_type = info & 0x3; + unsigned cache_scope = (info & 0xc) >> 2; + char *type, *scope; + + switch (cache_type) { + case 0: type = "separate data and instruction"; break; + case 1: type = "instruction"; break; + case 2: type = "data"; break; + case 3: type = "unified data and instruction"; break; + } + + switch (cache_scope) { + case 0: assert(0); // should never occur because cache exists + case 1: scope = "private"; break; + case 2: scope = "shared"; break; + case 3: scope = "reserved"; break; + } + + printf("L%u topology: %s; %s\n", level+1, type, scope); + printf("L%u cache line size data: %"PRId64"\n", level+1, + ecag(1, level, 0)); + printf("L%u cache line size insn: %"PRId64"\n", level+1, + ecag(1, level, 1)); + printf("L%u total cachesize data: %"PRId64"\n", level+1, + ecag(2, level, 0)); + printf("L%u total cachesize insn: %"PRId64"\n", level+1, + ecag(2, level, 1)); + printf("L%u set. assoc. data: %"PRId64"\n", level+1, + ecag(3, level, 0)); + printf("L%u set. assoc. insn: %"PRId64"\n", level+1, + ecag(3, level, 1)); + } + + return 0; +} diff --git a/none/tests/s390x/ecag.stderr.exp b/none/tests/s390x/ecag.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/s390x/ecag.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/s390x/ecag.stdout.exp-z10ec b/none/tests/s390x/ecag.stdout.exp-z10ec new file mode 100644 index 0000000000..13e78550ea --- /dev/null +++ b/none/tests/s390x/ecag.stdout.exp-z10ec @@ -0,0 +1,21 @@ +L1 topology: separate data and instruction; private +L1 cache line size data: 256 +L1 cache line size insn: 256 +L1 total cachesize data: 131072 +L1 total cachesize insn: 65536 +L1 set. assoc. data: 8 +L1 set. assoc. insn: 4 +L2 topology: unified data and instruction; private +L2 cache line size data: 256 +L2 cache line size insn: 256 +L2 total cachesize data: 3145728 +L2 total cachesize insn: 3145728 +L2 set. assoc. data: 12 +L2 set. assoc. insn: 12 +L3 topology: unified data and instruction; shared +L3 cache line size data: 256 +L3 cache line size insn: 256 +L3 total cachesize data: 50331648 +L3 total cachesize insn: 50331648 +L3 set. assoc. data: 24 +L3 set. assoc. insn: 24 diff --git a/none/tests/s390x/ecag.stdout.exp-z196 b/none/tests/s390x/ecag.stdout.exp-z196 new file mode 100644 index 0000000000..f44ea55635 --- /dev/null +++ b/none/tests/s390x/ecag.stdout.exp-z196 @@ -0,0 +1,28 @@ +L1 topology: separate data and instruction; private +L1 cache line size data: 256 +L1 cache line size insn: 256 +L1 total cachesize data: 131072 +L1 total cachesize insn: 65536 +L1 set. assoc. data: 8 +L1 set. assoc. insn: 4 +L2 topology: unified data and instruction; private +L2 cache line size data: 256 +L2 cache line size insn: 256 +L2 total cachesize data: 1572864 +L2 total cachesize insn: 1572864 +L2 set. assoc. data: 12 +L2 set. assoc. insn: 12 +L3 topology: unified data and instruction; shared +L3 cache line size data: 256 +L3 cache line size insn: 256 +L3 total cachesize data: 25165824 +L3 total cachesize insn: 25165824 +L3 set. assoc. data: 12 +L3 set. assoc. insn: 12 +L4 topology: unified data and instruction; shared +L4 cache line size data: 256 +L4 cache line size insn: 256 +L4 total cachesize data: 201326592 +L4 total cachesize insn: 201326592 +L4 set. assoc. data: 24 +L4 set. assoc. insn: 24 diff --git a/none/tests/s390x/ecag.vgtest b/none/tests/s390x/ecag.vgtest new file mode 100644 index 0000000000..f4abb7766d --- /dev/null +++ b/none/tests/s390x/ecag.vgtest @@ -0,0 +1,2 @@ +prereq: ../../../tests/s390x_features s390x-genins +prog: ecag diff --git a/none/tests/s390x/opcodes.h b/none/tests/s390x/opcodes.h index 8dcdea5aea..149dbe84fb 100644 --- a/none/tests/s390x/opcodes.h +++ b/none/tests/s390x/opcodes.h @@ -277,6 +277,7 @@ #define SHHLR(r3,r1,r2) RRF_R0RR2(b9d9,r3,0,r1,r2) #define SHY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,7b) #define SLAK(r1,r3,b2,dl2,dh2) RSY_RRRD(eb,r1,r3,b2,dl2,dh2,dd) +#define ECAG(r1,r3,b2,dl2,dh2) RSY_RRRD(eb,r1,r3,b2,dl2,dh2,4c) #define SLFI(r1,i2) RIL_RU(c2,r1,5,i2) #define SLGFI(r1,i2) RIL_RU(c2,r1,4,i2) #define SLGRK(r3,r1,r2) RRF_R0RR2(b9eb,r3,0,r1,r2)