From: Victor Do Nascimento Date: Wed, 3 May 2023 11:02:54 +0000 (+0100) Subject: aarch64: Add march flags for +the and +d128 arch extensions X-Git-Tag: basepoints/gcc-15~3907 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=16a05fac33ddde7a50da9cb937a9b83ea7c111f6;p=thirdparty%2Fgcc.git aarch64: Add march flags for +the and +d128 arch extensions Given the introduction of optional 128-bit page table descriptor and translation hardening extension support with the Arm9.4-a architecture, this introduces the relevant flags to enable the reading and writing of 128-bit system registers. The `+d128' -march modifier enables the use of the following ACLE builtin functions: * __uint128_t __arm_rsr128(const char *special_register); * void __arm_wsr128(const char *special_register, __uint128_t value); and defines the __ARM_FEATURE_SYSREG128 macro to 1. Finally, the `rcwmask_el1' and `rcwsmask_el1' 128-bit system register implementations are also reliant on the enablement of the `+the' flag, which is thus also implemented in this patch. gcc/ChangeLog: * config/aarch64/aarch64-c.cc (__ARM_FEATURE_SYSREG128): New. * config/aarch64/aarch64-arches.def (armv8.9-a): New. (armv9.4-a): Likewise. * config/aarch64/aarch64-option-extensions.def (d128): Likewise. (the): Likewise. * config/aarch64/aarch64.h (AARCH64_ISA_V9_4A): Likewise. (AARCH64_ISA_V8_9A): Likewise. (TARGET_ARMV9_4): Likewise. (AARCH64_ISA_D128): Likewise. (AARCH64_ISA_THE): Likewise. (TARGET_D128): Likewise. * doc/invoke.texi (AArch64 Options): Document new -march flags and extensions. --- diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index 6b9a19c490ba..1fe6b796001d 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -39,10 +39,12 @@ AARCH64_ARCH("armv8.5-a", generic_armv8_a, V8_5A, 8, (V8_4A, SB, SSBS AARCH64_ARCH("armv8.6-a", generic_armv8_a, V8_6A, 8, (V8_5A, I8MM, BF16)) AARCH64_ARCH("armv8.7-a", generic_armv8_a, V8_7A, 8, (V8_6A, LS64)) AARCH64_ARCH("armv8.8-a", generic_armv8_a, V8_8A, 8, (V8_7A, MOPS)) +AARCH64_ARCH("armv8.9-a", generic_armv8_a, V8_9A, 8, (V8_8A)) AARCH64_ARCH("armv8-r", generic_armv8_a, V8R , 8, (V8_4A)) AARCH64_ARCH("armv9-a", generic_armv9_a, V9A , 9, (V8_5A, SVE2)) AARCH64_ARCH("armv9.1-a", generic_armv9_a, V9_1A, 9, (V8_6A, V9A)) AARCH64_ARCH("armv9.2-a", generic_armv9_a, V9_2A, 9, (V8_7A, V9_1A)) AARCH64_ARCH("armv9.3-a", generic_armv9_a, V9_3A, 9, (V8_8A, V9_2A)) +AARCH64_ARCH("armv9.4-a", generic_armv9_a, V9_4A, 9, (V8_9A, V9_3A)) #undef AARCH64_ARCH diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc index 18422bb5663e..115a2a8b7568 100644 --- a/gcc/config/aarch64/aarch64-c.cc +++ b/gcc/config/aarch64/aarch64-c.cc @@ -254,6 +254,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_LS64, "__ARM_FEATURE_LS64", pfile); aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile); + aarch64_def_or_undef (TARGET_D128, "__ARM_FEATURE_SYSREG128", pfile); aarch64_def_or_undef (TARGET_SME, "__ARM_FEATURE_SME", pfile); aarch64_def_or_undef (TARGET_SME_I16I64, "__ARM_FEATURE_SME_I16I64", pfile); diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index c156d2ee76a1..97f03395ffca 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -159,4 +159,8 @@ AARCH64_OPT_EXTENSION("sme-f64f64", SME_F64F64, (SME), (), (), "") AARCH64_OPT_EXTENSION("sme2", SME2, (SME), (), (), "sme2") +AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128") + +AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index f277e784fc52..f0af0b43358e 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -254,13 +254,17 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) #define AARCH64_ISA_V8_7A (aarch64_isa_flags & AARCH64_FL_V8_7A) #define AARCH64_ISA_V8_8A (aarch64_isa_flags & AARCH64_FL_V8_8A) +#define AARCH64_ISA_V8_9A (aarch64_isa_flags & AARCH64_FL_V8_9A) #define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A) #define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A) #define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A) #define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A) +#define AARCH64_ISA_V9_4A (aarch64_isa_flags & AARCH64_FL_V9_4A) #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC) +#define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128) +#define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE) /* The current function is a normal non-streaming function. */ #define TARGET_NON_STREAMING (AARCH64_ISA_SM_OFF) @@ -450,6 +454,17 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; /* ARMv8.1-A Adv.SIMD support. */ #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) +/* Armv9.4-A features. */ +#define TARGET_ARMV9_4 (AARCH64_ISA_V9_4A) + +/* 128-bit System Registers and Instructions from Armv9.4-a are enabled + through +d128. */ +#define TARGET_D128 (AARCH64_ISA_D128) + +/* Armv8.9-A/9.4-A Translation Hardening Extension system registers are + enabled through +the. */ +#define TARGET_THE (AARCH64_ISA_THE) + /* Standard register usage. */ /* 31 64-bit general purpose registers R0-R30: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8e9204302d19..f5e5546080da 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21045,10 +21045,12 @@ and the features that they enable by default: @item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm} @item @samp{armv8.7-a} @tab Armv8.7-A @tab @samp{armv8.6-a}, @samp{+ls64} @item @samp{armv8.8-a} @tab Armv8.8-a @tab @samp{armv8.7-a}, @samp{+mops} +@item @samp{armv8.9-a} @tab Armv8.9-a @tab @samp{armv8.8-a} @item @samp{armv9-a} @tab Armv9-A @tab @samp{armv8.5-a}, @samp{+sve}, @samp{+sve2} @item @samp{armv9.1-a} @tab Armv9.1-A @tab @samp{armv9-a}, @samp{+bf16}, @samp{+i8mm} @item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+ls64} @item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops} +@item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a} @item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r} @end multitable @@ -21359,6 +21361,11 @@ Enable the FEAT_SME_I16I64 extension to SME. Enable the FEAT_SME_F64F64 extension to SME. +@item sme2 Enable the Scalable Matrix Extension 2. This also enables SME instructions. +@item d128 +Enable support for 128-bit system register read/write instructions. +@item the +Enable support for Armv8.9-a/9.4-a translation hardening extension. + @end table Feature @option{crypto} implies @option{aes}, @option{sha2}, and @option{simd},