From: Christophe Lyon Date: Mon, 13 Feb 2023 18:09:08 +0000 (+0000) Subject: arm: [MVE intrinsics] factorize vmaxvq vminvq vmaxavq vminavq X-Git-Tag: basepoints/gcc-15~9513 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=16c5aca6a13ffd1d94bf8a3dc7a16facc8843e60;p=thirdparty%2Fgcc.git arm: [MVE intrinsics] factorize vmaxvq vminvq vmaxavq vminavq Factorize vmaxvq vminvq vmaxavq vminavq so that they use the same pattern. 2022-09-08 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_VMAXVQ_VMINVQ, MVE_VMAXVQ_VMINVQ_P): New. (mve_insn): Add vmaxav, vmaxv, vminav, vminv. (supf): Add VMAXAVQ_S, VMAXAVQ_P_S, VMINAVQ_S, VMINAVQ_P_S. * config/arm/mve.md (mve_vmaxavq_s, mve_vmaxvq_) (mve_vminavq_s, mve_vminvq_): Merge into ... (@mve_q_): ... this. (mve_vmaxavq_p_s, mve_vmaxvq_p_) (mve_vminavq_p_s, mve_vminvq_p_): Merge into ... (@mve_q_p_): ... this. --- diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index e82ff0d5d9bf..5bb7e2be7c86 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -578,6 +578,20 @@ VCREATEQ_F ]) +(define_int_iterator MVE_VMAXVQ_VMINVQ [ + VMAXAVQ_S + VMAXVQ_S VMAXVQ_U + VMINAVQ_S + VMINVQ_S VMINVQ_U + ]) + +(define_int_iterator MVE_VMAXVQ_VMINVQ_P [ + VMAXAVQ_P_S + VMAXVQ_P_S VMAXVQ_P_U + VMINAVQ_P_S + VMINVQ_P_S VMINVQ_P_U + ]) + (define_int_iterator MVE_MOVN [ VMOVNBQ_S VMOVNBQ_U VMOVNTQ_S VMOVNTQ_U @@ -627,8 +641,16 @@ (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub") (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub") (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub") + (VMAXAVQ_P_S "vmaxav") + (VMAXAVQ_S "vmaxav") (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax") + (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv") + (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv") + (VMINAVQ_P_S "vminav") + (VMINAVQ_S "vminav") (VMINQ_M_S "vmin") (VMINQ_M_U "vmin") + (VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv") + (VMINVQ_S "vminv") (VMINVQ_U "vminv") (VMLAQ_M_N_S "vmla") (VMLAQ_M_N_U "vmla") (VMLASQ_M_N_S "vmlas") (VMLASQ_M_N_U "vmlas") (VMOVNBQ_M_S "vmovnb") (VMOVNBQ_M_U "vmovnb") @@ -1992,6 +2014,10 @@ (VQMOVUNBQ_S "s") (VQMOVUNTQ_M_S "s") (VQMOVUNTQ_S "s") + (VMAXAVQ_S "s") + (VMAXAVQ_P_S "s") + (VMINAVQ_S "s") + (VMINAVQ_P_S "s") ]) ;; Both kinds of return insn. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 98728e6f3ef6..715e85c99988 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -962,21 +962,6 @@ [(set_attr "type" "mve_move") ]) -;; -;; [vmaxavq_s]) -;; -(define_insn "mve_vmaxavq_s" - [ - (set (match_operand: 0 "s_register_operand" "=r") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VMAXAVQ_S)) - ] - "TARGET_HAVE_MVE" - "vmaxav.s%#\t%0, %q2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vmaxq_u, vmaxq_s] ;; [vminq_s, vminq_u] @@ -994,17 +979,20 @@ ;; -;; [vmaxvq_u, vmaxvq_s]) +;; [vmaxavq_s] +;; [vmaxvq_u, vmaxvq_s] +;; [vminavq_s] +;; [vminvq_u, vminvq_s] ;; -(define_insn "mve_vmaxvq_" +(define_insn "@mve_q_" [ (set (match_operand: 0 "s_register_operand" "=r") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w")] - VMAXVQ)) + MVE_VMAXVQ_VMINVQ)) ] "TARGET_HAVE_MVE" - "vmaxv.%#\t%0, %q2" + ".%#\t%0, %q2" [(set_attr "type" "mve_move") ]) @@ -1023,36 +1011,6 @@ [(set_attr "type" "mve_move") ]) -;; -;; [vminavq_s]) -;; -(define_insn "mve_vminavq_s" - [ - (set (match_operand: 0 "s_register_operand" "=r") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VMINAVQ_S)) - ] - "TARGET_HAVE_MVE" - "vminav.s%#\t%0, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vminvq_u, vminvq_s]) -;; -(define_insn "mve_vminvq_" - [ - (set (match_operand: 0 "s_register_operand" "=r") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VMINVQ)) - ] - "TARGET_HAVE_MVE" - "vminv.%#\t%0, %q2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vmladavq_u, vmladavq_s]) ;; @@ -2366,34 +2324,21 @@ (set_attr "length""8")]) ;; -;; [vmaxavq_p_s]) -;; -(define_insn "mve_vmaxavq_p_s" - [ - (set (match_operand: 0 "s_register_operand" "=r") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VMAXAVQ_P_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vmaxavt.s%# %0, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vmaxvq_p_u, vmaxvq_p_s]) +;; [vmaxavq_p_s] +;; [vmaxvq_p_u, vmaxvq_p_s] +;; [vminavq_p_s] +;; [vminvq_p_s, vminvq_p_u] ;; -(define_insn "mve_vmaxvq_p_" +(define_insn "@mve_q_p_" [ (set (match_operand: 0 "s_register_operand" "=r") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up")] - VMAXVQ_P)) + MVE_VMAXVQ_VMINVQ_P)) ] "TARGET_HAVE_MVE" - "vpst\;vmaxvt.%# %0, %q2" + "vpst\;t.%#\t%0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -2413,38 +2358,6 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vminavq_p_s]) -;; -(define_insn "mve_vminavq_p_s" - [ - (set (match_operand: 0 "s_register_operand" "=r") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VMINAVQ_P_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vminavt.s%# %0, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vminvq_p_s, vminvq_p_u]) -;; -(define_insn "mve_vminvq_p_" - [ - (set (match_operand: 0 "s_register_operand" "=r") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "vpr_register_operand" "Up")] - VMINVQ_P)) - ] - "TARGET_HAVE_MVE" - "vpst\;vminvt.%#\t%0, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vmladavaq_u, vmladavaq_s]) ;;