From: Alan Modra Date: Tue, 18 Aug 2020 23:17:35 +0000 (+0930) Subject: Correct vcmpsq, vcmpuq and xvtlsbb BF field X-Git-Tag: binutils-2_35_2~169 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=172234e1fab477ba36ec292913b1f13ef6b94783;p=thirdparty%2Fbinutils-gdb.git Correct vcmpsq, vcmpuq and xvtlsbb BF field These shouldn't be optional. The record form of vector instructions set CR6, giving an expectation that omitting BF should be the same as specifying CR6. opcodes/ * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq, vcmpuq and xvtlsbb. gas/ * testsuite/gas/ppc/int128.s: Correct vcmpuq. * testsuite/gas/ppc/int128.d: Update. * testsuite/gas/ppc/xvtlsbb.d: Update. (cherry picked from commit 18a8a00ebe3159b65798c6132cb5f93ff4ef6c17) --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 3d5376df89e..fa9e9d1ff23 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,6 +1,11 @@ 2020-09-24 Alan Modra Apply from master + 2020-08-19 Alan Modra + * testsuite/gas/ppc/int128.s: Correct vcmpuq. + * testsuite/gas/ppc/int128.d: Update. + * testsuite/gas/ppc/xvtlsbb.d: Update. + 2020-08-10 Alan Modra * testsuite/gas/ppc/power8.d, * testsuite/gas/ppc/power8.s: Add miso. diff --git a/gas/testsuite/gas/ppc/int128.d b/gas/testsuite/gas/ppc/int128.d index c9f14d3360d..d7410345ad7 100644 --- a/gas/testsuite/gas/ppc/int128.d +++ b/gas/testsuite/gas/ppc/int128.d @@ -20,7 +20,7 @@ Disassembly of section \.text: .*: (13 9d f7 0b|0b f7 9d 13) vmodsq v28,v29,v30 .*: (13 e0 0e 0b|0b 0e e0 13) vmoduq v31,v0,v1 .*: (10 5b 1e 02|02 1e 5b 10) vextsd2q v2,v3 -.*: (10 04 29 01|01 29 04 10) vcmpuq v4,v5 +.*: (10 04 29 01|01 29 04 10) vcmpuq cr0,v4,v5 .*: (10 86 39 41|41 39 86 10) vcmpsq cr1,v6,v7 .*: (11 09 51 c7|c7 51 09 11) vcmpequq v8,v9,v10 .*: (11 6c 6d c7|c7 6d 6c 11) vcmpequq. v11,v12,v13 diff --git a/gas/testsuite/gas/ppc/int128.s b/gas/testsuite/gas/ppc/int128.s index 4dce648c36f..4561cfe9ee6 100644 --- a/gas/testsuite/gas/ppc/int128.s +++ b/gas/testsuite/gas/ppc/int128.s @@ -12,7 +12,7 @@ _start: vmodsq 28,29,30 vmoduq 31,0,1 vextsd2q 2,3 - vcmpuq 4,5 + vcmpuq 0,4,5 vcmpsq 1,6,7 vcmpequq 8,9,10 vcmpequq. 11,12,13 diff --git a/gas/testsuite/gas/ppc/xvtlsbb.d b/gas/testsuite/gas/ppc/xvtlsbb.d index 1627d7afc6d..8aa83dd62c7 100644 --- a/gas/testsuite/gas/ppc/xvtlsbb.d +++ b/gas/testsuite/gas/ppc/xvtlsbb.d @@ -7,7 +7,7 @@ Disassembly of section \.text: 0+0 <_start>: -.*: (f0 02 ff 6e|6e ff 02 f0) xvtlsbb vs63 +.*: (f0 02 ff 6e|6e ff 02 f0) xvtlsbb cr0,vs63 .*: (f0 82 07 6c|6c 07 82 f0) xvtlsbb cr1,vs0 .*: (f1 02 f7 6e|6e f7 02 f1) xvtlsbb cr2,vs62 .*: (f1 82 0f 6c|6c 0f 82 f1) xvtlsbb cr3,vs1 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 06d136d4805..6e1fb264f94 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,10 @@ 2020-09-24 Alan Modra Apply from master + 2020-08-19 Alan Modra + * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq, + vcmpuq and xvtlsbb. + 2020-08-10 Alan Modra * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended instructions. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 4471b0f2bc7..d15bde1326e 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4441,7 +4441,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, -{"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {OBF, VA, VB}}, +{"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {BF, VA, VB}}, {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}}, @@ -4459,7 +4459,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, -{"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {OBF, VA, VB}}, +{"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {BF, VA, VB}}, {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}}, @@ -8455,7 +8455,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"xxgenpcvdm", X(60,949), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, -{"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK, POWER10, PPCVLE, {OBF, XB6}}, +{"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK, POWER10, PPCVLE, {BF, XB6}}, {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},