From: Andrew Pinski <quic_apinski@quicinc.com>
Date: Mon, 17 Jun 2024 23:45:34 +0000 (-0700)
Subject: aarch64: Add testcase for PR97405
X-Git-Tag: basepoints/gcc-16~8166
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=17979deb15d34dd4f036ca93d2977d0fc4d556a7;p=thirdparty%2Fgcc.git

aarch64: Add testcase for PR97405

This aarch64 sve specific code was fixed by r15-917-gc9842f99042454
which added a riscv specific testcase so adding an aarch64 one to test
the fix does not regress is a good idea.

Committed as obvious after testing the testcase for aarch64-linux-gnu.

	PR tree-optimization/97405

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/sve/pr97405-1.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
---

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c
new file mode 100644
index 00000000000..5efa32c9928
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.2-a+sve -O2" }
+/* PR tree-optimization/97405 */
+#include "arm_sve.h"
+
+void
+a (svuint8x3_t b, unsigned char *p, int c) {
+  if (c)
+    svst1_u8(svptrue_pat_b8(SV_VL16), p, svget3_u8(b, 1));
+  else
+    svst1_u8(svwhilelt_b8(6, 6), p, svget3_u8(b, 1));
+}
+