From: Hans Kristian Rosbach Date: Sat, 4 Feb 2023 21:19:40 +0000 (+0100) Subject: Remove FORCE_TZCNT/X86_NOCHECK_TZCNT X-Git-Tag: 2.1.0-beta1~68 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=17d98072a97d5b29c7b8f24133f2abf263fa93b4;p=thirdparty%2Fzlib-ng.git Remove FORCE_TZCNT/X86_NOCHECK_TZCNT --- diff --git a/CMakeLists.txt b/CMakeLists.txt index 48e09d521..27ce9f477 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -112,7 +112,6 @@ elseif(BASEARCH_S360_FOUND) option(WITH_DFLTCC_INFLATE "Build with DFLTCC intrinsics for decompression on IBM Z" OFF) option(WITH_CRC32_VX "Build with vectorized CRC32 on IBM Z" ON) elseif(BASEARCH_X86_FOUND) - option(FORCE_TZCNT "Always assume CPU is TZCNT capable" OFF) option(WITH_AVX2 "Build with AVX2" ON) option(WITH_AVX512 "Build with AVX512" ON) option(WITH_AVX512VNNI "Build with AVX512 VNNI extensions" ON) @@ -819,10 +818,6 @@ if(WITH_OPTIM) set(WITH_SSE4 OFF) endif() endif() - if(FORCE_TZCNT) - add_definitions(-DX86_NOCHECK_TZCNT) - endif() - add_feature_info(FORCE_TZCNT FORCE_TZCNT "Assume CPU is TZCNT capable") if(WITH_SSE2) check_sse2_intrinsics() if(HAVE_SSE2_INTRIN) diff --git a/README.md b/README.md index a40980a07..5b8e8ccdc 100644 --- a/README.md +++ b/README.md @@ -209,7 +209,6 @@ Advanced Build Options | CMake | configure | Description | Default | |:--------------------------------|:----------------------|:--------------------------------------------------------------------|------------------------| | FORCE_SSE2 | --force-sse2 | Skip runtime check for SSE2 instructions (Always on for x86_64) | OFF (x86) | -| FORCE_TZCNT | --force-tzcnt | Skip runtime check for TZCNT instructions | OFF | | WITH_AVX2 | | Build with AVX2 intrinsics | ON | | WITH_AVX512 | | Build with AVX512 intrinsics | ON | | WITH_AVX512VNNI | | Build with AVX512VNNI intrinsics | ON | diff --git a/arch/x86/x86_features.c b/arch/x86/x86_features.c index 4c7563eab..d1ac51c55 100644 --- a/arch/x86/x86_features.c +++ b/arch/x86/x86_features.c @@ -122,7 +122,4 @@ void Z_INTERNAL x86_check_features(void) { x86_cpu_has_avx512vnni = 0; x86_cpu_has_vpclmulqdq = 0; } -#ifdef X86_NOCHECK_TZCNT - Assert(!!x86_cpu_has_tzcnt, "TZCNT is not available"); -#endif } diff --git a/configure b/configure index 9cd570239..c0f9524b5 100755 --- a/configure +++ b/configure @@ -103,7 +103,6 @@ buildcrc32vx=1 floatabi= native=0 forcesse2=0 -forcetzcnt=0 # For CPUs that can benefit from AVX512, it seems GCC generates suboptimal # instruction scheduling unless you specify a reasonable -mtune= target avx512flag="-mavx512f -mavx512dq -mavx512bw -mavx512vl -mtune=cascadelake" @@ -177,7 +176,6 @@ case "$1" in echo ' [--without-crc32-vx] Build without vectorized CRC32 on IBM Z' | tee -a configure.log echo ' [--with-reduced-mem] Reduced memory usage for special cases (reduces performance)' | tee -a configure.log echo ' [--force-sse2] Assume SSE2 instructions are always available (disabled by default on x86, enabled on x86_64)' | tee -a configure.log - echo ' [--force-tzcnt] Assume TZCNT instructions are always available (disabled by default)' | tee -a configure.log echo ' [--native] Compiles with full instruction set supported on this host' | tee -a configure.log exit 0 ;; -p*=* | --prefix=*) prefix=$(echo $1 | sed 's/.*=//'); shift ;; @@ -211,7 +209,6 @@ case "$1" in --without-crc32-vx) buildcrc32vx=0; shift ;; --with-reduced-mem) reducedmem=1; shift ;; --force-sse2) forcesse2=1; shift ;; - --force-tzcnt) forcetzcnt=1; shift ;; -n | --native) native=1; shift ;; -a*=* | --archs=*) ARCHS=$(echo $1 | sed 's/.*=//'); shift ;; --sysconfdir=*) echo "ignored option: --sysconfdir" | tee -a configure.log; shift ;; @@ -1652,11 +1649,6 @@ case "${ARCH}" in if test ${HAVE_XSAVE_INTRIN} -eq 0; then xsaveflag="" fi - - if test $forcetzcnt -eq 1; then - CFLAGS="${CFLAGS} -DX86_NOCHECK_TZCNT" - SFLAGS="${SFLAGS} -DX86_NOCHECK_TZCNT" - fi fi ;;