From: Julian Seward Date: Mon, 24 Jul 2006 08:51:16 +0000 (+0000) Subject: Implement SSE2 'psadbw'. Fixes #128917. X-Git-Tag: svn/VALGRIND_3_3_1^2~111 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=186baadc292d80641fa418197ad3e9563d8417d6;p=thirdparty%2Fvalgrind.git Implement SSE2 'psadbw'. Fixes #128917. git-svn-id: svn://svn.valgrind.org/vex/trunk@1632 --- diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c index 80c67b3dd9..a0f097a51b 100644 --- a/VEX/priv/guest-amd64/toIR.c +++ b/VEX/priv/guest-amd64/toIR.c @@ -11111,6 +11111,54 @@ DisResult disInstr_AMD64_WRK ( goto decode_success; } + /* 66 0F F6 = PSADBW -- 2 x (8x8 -> 48 zeroes ++ u16) Sum Abs Diffs + from E(xmm or mem) to G(xmm) */ + if (have66noF2noF3(pfx) && sz == 2 + && insn[0] == 0x0F && insn[1] == 0xF6) { + IRTemp s1V = newTemp(Ity_V128); + IRTemp s2V = newTemp(Ity_V128); + IRTemp dV = newTemp(Ity_V128); + IRTemp s1Hi = newTemp(Ity_I64); + IRTemp s1Lo = newTemp(Ity_I64); + IRTemp s2Hi = newTemp(Ity_I64); + IRTemp s2Lo = newTemp(Ity_I64); + IRTemp dHi = newTemp(Ity_I64); + IRTemp dLo = newTemp(Ity_I64); + modrm = insn[2]; + if (epartIsReg(modrm)) { + assign( s1V, getXMMReg(eregOfRexRM(pfx,modrm)) ); + delta += 2+1; + DIP("psadbw %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)), + nameXMMReg(gregOfRexRM(pfx,modrm))); + } else { + addr = disAMode ( &alen, pfx, delta+2, dis_buf, 0 ); + assign( s1V, loadLE(Ity_V128, mkexpr(addr)) ); + delta += 2+alen; + DIP("psadbw %s,%s\n", dis_buf, + nameXMMReg(gregOfRexRM(pfx,modrm))); + } + assign( s2V, getXMMReg(gregOfRexRM(pfx,modrm)) ); + assign( s1Hi, unop(Iop_V128HIto64, mkexpr(s1V)) ); + assign( s1Lo, unop(Iop_V128to64, mkexpr(s1V)) ); + assign( s2Hi, unop(Iop_V128HIto64, mkexpr(s2V)) ); + assign( s2Lo, unop(Iop_V128to64, mkexpr(s2V)) ); + assign( dHi, mkIRExprCCall( + Ity_I64, 0/*regparms*/, + "amd64g_calculate_mmx_psadbw", + &amd64g_calculate_mmx_psadbw, + mkIRExprVec_2( mkexpr(s1Hi), mkexpr(s2Hi)) + )); + assign( dLo, mkIRExprCCall( + Ity_I64, 0/*regparms*/, + "amd64g_calculate_mmx_psadbw", + &amd64g_calculate_mmx_psadbw, + mkIRExprVec_2( mkexpr(s1Lo), mkexpr(s2Lo)) + )); + assign( dV, binop(Iop_64HLtoV128, mkexpr(dHi), mkexpr(dLo))) ; + putXMMReg(gregOfRexRM(pfx,modrm), mkexpr(dV)); + goto decode_success; + } + /* 66 0F 70 = PSHUFD -- rearrange 4x32 from E(xmm or mem) to G(xmm) */ if (have66noF2noF3(pfx) && sz == 2 && insn[0] == 0x0F && insn[1] == 0x70) {