From: Kito Cheng <kito.cheng@sifive.com>
Date: Fri, 2 Jul 2021 02:19:30 +0000 (+0800)
Subject: docs: Add 'S' to Machine Constraints for RISC-V
X-Git-Tag: basepoints/gcc-13~6045
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=18a463bb666cc8f3421589e7641ec617acb84741;p=thirdparty%2Fgcc.git

docs: Add 'S' to Machine Constraints for RISC-V

It was undocument before, but it might used in linux kernel for resolve
code model issue, so LLVM community suggest we should document that,
so that make it become supported/documented/non-internal machine constraints.

gcc/ChangeLog:

	PR target/101275
	* config/riscv/constraints.md ("S"): Update description and remove
	@internal.
	* doc/md.texi (Machine Constraints): Document the 'S' constraints
	for RISC-V.
---

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 8c15c6c0486d..c87d5b796a54 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -67,8 +67,7 @@
        (match_test "GET_CODE(XEXP(op,0)) == REG")))
 
 (define_constraint "S"
-  "@internal
-   A constant call address."
+  "A constraint that matches an absolute symbolic address."
   (match_operand 0 "absolute_symbolic_operand"))
 
 (define_constraint "U"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 0fe70b7ea400..8225a768a5cc 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3536,6 +3536,9 @@ A 5-bit unsigned immediate for CSR access instructions.
 @item A
 An address that is held in a general-purpose register.
 
+@item S
+A constraint that matches an absolute symbolic address.
+
 @end table
 
 @item RX---@file{config/rx/constraints.md}