From: Jan Hubicka Date: Thu, 7 Aug 2008 07:35:51 +0000 (+0200) Subject: optabs.c (emit_unop_insn): Break out to ... X-Git-Tag: releases/gcc-4.4.0~3268 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=18bd082d900d085c09132cc66cec118dd2037fc2;p=thirdparty%2Fgcc.git optabs.c (emit_unop_insn): Break out to ... * optabs.c (emit_unop_insn): Break out to ... (maybe_emit_unop_insn): ... this one. (expand_sfix_optab): Use maybe variant. * optabs.h (maybe_emit_unop_insn): Declare. * i386.md (mov0 patterns): Enable by default. (FP conversion expanders): Disable expansion of code expanding sequences when instruction should be optimized for size. (single strinop patterns): Enable when optimizing for size. (string expanders): Disable expanding of code expanding sequences when optimizning instruction for size. * i386.c (ix86_expand_vector_move_misalign): Do code size optimization per BB basis. (ix86_fp_comparison_sahf_cost): Likewise. (ix86_expand_branch): Likewise. (ix86_expand_ashl_const): Likewise. (ix86_split_ashl): Likewise. (ix86_expand_strlen): Likewise. (ix86_emit_fp_unordered_jump): Likewie. From-SVN: r138835 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f461410957e9..8520ddf28a9a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2008-08-06 Jan Hubicka + + * optabs.c (emit_unop_insn): Break out to ... + (maybe_emit_unop_insn): ... this one. + (expand_sfix_optab): Use maybe variant. + * optabs.h (maybe_emit_unop_insn): Declare. + + * i386.md (mov0 patterns): Enable by default. + (FP conversion expanders): Disable expansion of code expanding + sequences when instruction should be optimized for size. + (single strinop patterns): Enable when optimizing for size. + (string expanders): Disable expanding of code expanding sequences + when optimizning instruction for size. + * i386.c (ix86_expand_vector_move_misalign): Do code size optimization + per BB basis. + (ix86_fp_comparison_sahf_cost): Likewise. + (ix86_expand_branch): Likewise. + (ix86_expand_ashl_const): Likewise. + (ix86_split_ashl): Likewise. + (ix86_expand_strlen): Likewise. + (ix86_emit_fp_unordered_jump): Likewie. + 2008-08-06 Kaveh R. Ghazi * c-common.c: Fix typo. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 37f00faff092..3ebe2627ce69 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -11808,7 +11808,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) if (MEM_P (op1)) { /* If we're optimizing for size, movups is the smallest. */ - if (optimize_size) + if (optimize_insn_for_size_p ()) { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); @@ -11890,7 +11890,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) else if (MEM_P (op0)) { /* If we're optimizing for size, movups is the smallest. */ - if (optimize_size) + if (optimize_insn_for_size_p ()) { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); @@ -13094,7 +13094,7 @@ ix86_fp_comparison_sahf_cost (enum rtx_code code) enum rtx_code bypass_code, first_code, second_code; /* Return arbitrarily high cost when instruction is not preferred - this avoids gcc from using it. */ - if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))) + if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))) return 1024; ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3; @@ -13579,7 +13579,7 @@ ix86_expand_branch (enum rtx_code code, rtx label) optimizing for size. */ if ((code == EQ || code == NE) - && (!optimize_size + && (!optimize_insn_for_size_p () || hi[1] == const0_rtx || lo[1] == const0_rtx)) { rtx xor0, xor1; @@ -15631,7 +15631,7 @@ ix86_split_long_move (rtx operands[]) } /* If optimizing for size, attempt to locally unCSE nonzero constants. */ - if (optimize_size) + if (optimize_insn_for_size_p ()) { for (j = 0; j < nparts - 1; j++) if (CONST_INT_P (operands[6 + j]) @@ -15662,7 +15662,7 @@ ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode) ? gen_addsi3 : gen_adddi3) (operand, operand, operand)); } - else if (!optimize_size + else if (!optimize_insn_for_size_p () && count * ix86_cost->add <= ix86_cost->shift_const) { int i; @@ -15745,7 +15745,7 @@ ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode) { rtx x; - if (TARGET_PARTIAL_REG_STALL && !optimize_size) + if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ()) x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]); else x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]); @@ -15777,7 +15777,7 @@ ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode) /* For -1 << N, we can avoid the shld instruction, because we know that we're shifting 0...31/63 ones into a -1. */ emit_move_insn (low[0], constm1_rtx); - if (optimize_size) + if (optimize_insn_for_size_p ()) emit_move_insn (high[0], low[0]); else emit_move_insn (high[0], constm1_rtx); @@ -16642,7 +16642,7 @@ decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset, if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg)) return stringop_alg; /* rep; movq or rep; movl is the smallest variant. */ - else if (optimize_size) + else if (optimize_insn_for_size_p ()) { if (!count || (count & 3)) return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte; @@ -17557,7 +17557,7 @@ ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align) if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && !TARGET_INLINE_ALL_STRINGOPS - && !optimize_size + && !optimize_insn_for_size_p () && (!CONST_INT_P (align) || INTVAL (align) < 4)) return 0; @@ -17565,7 +17565,7 @@ ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align) scratch1 = gen_reg_rtx (Pmode); if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 - && !optimize_size) + && !optimize_insn_for_size_p ()) { /* Well it seems that some optimizer does not combine a call like foo(strlen(bar), strlen(bar)); @@ -23185,7 +23185,7 @@ static tree ix86_builtin_reciprocal (unsigned int fn, bool md_fn, bool sqrt ATTRIBUTE_UNUSED) { - if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size + if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p () && flag_finite_math_only && !flag_trapping_math && flag_unsafe_math_optimizations)) return NULL_TREE; @@ -26137,7 +26137,7 @@ ix86_emit_fp_unordered_jump (rtx label) emit_insn (gen_x86_fnstsw_1 (reg)); - if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)) + if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())) { emit_insn (gen_x86_sahf_1 (reg)); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2e737b10abef..1321fed647ba 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1419,7 +1419,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "const0_operand" "")) (clobber (reg:CC FLAGS_REG))] - "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" + "reload_completed" "xor{l}\t%0, %0" [(set_attr "type" "alu1") (set_attr "mode" "SI") @@ -1430,8 +1430,7 @@ (match_operand:SI 1 "immediate_operand" "i")) (clobber (reg:CC FLAGS_REG))] "reload_completed - && operands[1] == constm1_rtx - && (TARGET_MOVE_M1_VIA_OR || optimize_size)" + && operands[1] == constm1_rtx" { operands[1] = constm1_rtx; return "or{l}\t{%1, %0|%0, %1}"; @@ -1710,8 +1709,7 @@ [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) (match_operand:HI 1 "const0_operand" "")) (clobber (reg:CC FLAGS_REG))] - "reload_completed - && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)" + "reload_completed" "xor{w}\t%0, %0" [(set_attr "type" "alu1") (set_attr "mode" "HI") @@ -1867,7 +1865,7 @@ [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q")) (match_operand:QI 1 "const0_operand" "")) (clobber (reg:CC FLAGS_REG))] - "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" + "reload_completed" "xor{b}\t%0, %0" [(set_attr "type" "alu1") (set_attr "mode" "QI") @@ -2193,7 +2191,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const0_operand" "")) (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size) + "TARGET_64BIT && reload_completed" "xor{l}\t%k0, %k0"; [(set_attr "type" "alu1") @@ -2204,7 +2202,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const_int_operand" "i")) (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT && (TARGET_MOVE_M1_VIA_OR || optimize_size) + "TARGET_64BIT && reload_completed && operands[1] == constm1_rtx" { @@ -4502,13 +4500,16 @@ (use (match_dup 2)) (clobber (match_scratch: 3 "")) (clobber (match_scratch: 4 ""))])] - "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size" + "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH" { enum machine_mode mode = mode; enum machine_mode vecmode = mode; REAL_VALUE_TYPE TWO31r; rtx two31; + if (optimize_insn_for_size_p ()) + FAIL; + real_ldexp (&TWO31r, &dconst1, 31); two31 = const_double_from_real_value (TWO31r, mode); two31 = ix86_build_const_vector (mode, true, two31); @@ -8215,7 +8216,7 @@ (match_operand:SF 2 "nonimmediate_operand" "")))] "TARGET_80387 || TARGET_SSE_MATH" { - if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size + if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p () && flag_finite_math_only && !flag_trapping_math && flag_unsafe_math_optimizations) { @@ -16911,10 +16912,13 @@ UNSPEC_FPATAN)) (clobber (match_scratch:XF 6 ""))])] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { int i; + if (optimize_insn_for_size_p ()) + FAIL; + for (i = 2; i < 6; i++) operands[i] = gen_reg_rtx (XFmode); @@ -16927,11 +16931,14 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); rtx op1 = gen_reg_rtx (XFmode); + if (optimize_insn_for_size_p ()) + FAIL; + emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_asinxf2 (op0, op1)); emit_insn (gen_truncxf2_i387_noop (operands[0], op0)); @@ -16949,10 +16956,13 @@ UNSPEC_FPATAN)) (clobber (match_scratch:XF 6 ""))])] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { int i; + if (optimize_insn_for_size_p ()) + FAIL; + for (i = 2; i < 6; i++) operands[i] = gen_reg_rtx (XFmode); @@ -16965,11 +16975,14 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); rtx op1 = gen_reg_rtx (XFmode); + if (optimize_insn_for_size_p ()) + FAIL; + emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_acosxf2 (op0, op1)); emit_insn (gen_truncxf2_i387_noop (operands[0], op0)); @@ -17124,8 +17137,11 @@ [(use (match_operand:XF 0 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { + if (optimize_insn_for_size_p ()) + FAIL; + ix86_emit_i387_log1p (operands[0], operands[1]); DONE; }) @@ -17136,9 +17152,14 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); + rtx op0; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]); @@ -17206,10 +17227,15 @@ [(use (match_operand:SI 0 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_fxtractxf3_i387 (op0, op1, operands[1])); emit_insn (gen_fix_truncxfsi2 (operands[0], op1)); @@ -17222,10 +17248,15 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_fxtract_extendxf3_i387 (op0, op1, operands[1])); emit_insn (gen_fix_truncxfsi2 (operands[0], op1)); @@ -17270,10 +17301,13 @@ (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE_EXP))])] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { int i; + if (optimize_insn_for_size_p ()) + FAIL; + for (i = 3; i < 10; i++) operands[i] = gen_reg_rtx (XFmode); @@ -17284,9 +17318,14 @@ [(use (match_operand:XF 0 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op2 = gen_reg_rtx (XFmode); + rtx op2; + + if (optimize_insn_for_size_p ()) + FAIL; + + op2 = gen_reg_rtx (XFmode); emit_move_insn (op2, standard_80387_constant_rtx (5)); /* fldl2e */ emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); @@ -17299,10 +17338,15 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_expxf2 (op0, op1)); @@ -17314,9 +17358,14 @@ [(use (match_operand:XF 0 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op2 = gen_reg_rtx (XFmode); + rtx op2; + + if (optimize_insn_for_size_p ()) + FAIL; + + op2 = gen_reg_rtx (XFmode); emit_move_insn (op2, standard_80387_constant_rtx (6)); /* fldl2t */ emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); @@ -17329,10 +17378,15 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_exp10xf2 (op0, op1)); @@ -17344,9 +17398,14 @@ [(use (match_operand:XF 0 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op2 = gen_reg_rtx (XFmode); + rtx op2; + + if (optimize_insn_for_size_p ()) + FAIL; + + op2 = gen_reg_rtx (XFmode); emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */ emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); @@ -17359,10 +17418,15 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_exp2xf2 (op0, op1)); @@ -17394,10 +17458,13 @@ (set (match_operand:XF 0 "register_operand" "") (plus:XF (match_dup 12) (match_dup 7)))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { int i; + if (optimize_insn_for_size_p ()) + FAIL; + for (i = 2; i < 13; i++) operands[i] = gen_reg_rtx (XFmode); @@ -17413,10 +17480,15 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_expm1xf2 (op0, op1)); @@ -17435,8 +17507,11 @@ (unspec:XF [(match_dup 1) (match_dup 3)] UNSPEC_FSCALE_EXP))])] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { + if (optimize_insn_for_size_p ()) + FAIL; + operands[3] = gen_reg_rtx (XFmode); operands[4] = gen_reg_rtx (XFmode); }) @@ -17448,10 +17523,15 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_ldexpxf3 (op0, op1, operands[2])); @@ -17468,8 +17548,11 @@ (unspec:XF [(match_dup 1) (match_dup 2)] UNSPEC_FSCALE_EXP))])] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { + if (optimize_insn_for_size_p ()) + FAIL; + operands[3] = gen_reg_rtx (XFmode); }) @@ -17480,11 +17563,16 @@ "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); - rtx op2 = gen_reg_rtx (XFmode); + rtx op0, op1, op2; + + if (optimize_insn_for_size_p ()) + FAIL; + + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); + op2 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_extendxf2 (op2, operands[2])); @@ -17523,13 +17611,13 @@ || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !flag_trapping_math - && (TARGET_ROUND || !optimize_size))" + && !flag_trapping_math)" { if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !flag_trapping_math - && (TARGET_ROUND || !optimize_size)) + && !flag_trapping_math) { + if (!TARGET_ROUND && optimize_insn_for_size_p ()) + FAIL; if (TARGET_ROUND) emit_insn (gen_sse4_1_round2 (operands[0], operands[1], GEN_INT (0x04))); @@ -17553,9 +17641,10 @@ [(match_operand:MODEF 0 "register_operand" "") (match_operand:MODEF 1 "nonimmediate_operand" "")] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !flag_trapping_math && !flag_rounding_math - && !optimize_size" + && !flag_trapping_math && !flag_rounding_math" { + if (optimize_insn_for_size_p ()) + FAIL; if (TARGET_64BIT || (mode != DFmode)) ix86_expand_round (operand0, operand1); else @@ -17706,9 +17795,10 @@ (match_operand:MODEF 1 "register_operand" "")] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && ((mode != DImode) || TARGET_64BIT) - && !flag_trapping_math && !flag_rounding_math - && !optimize_size" + && !flag_trapping_math && !flag_rounding_math" { + if (optimize_insn_for_size_p ()) + FAIL; ix86_expand_lround (operand0, operand1); DONE; }) @@ -17756,8 +17846,10 @@ [(use (match_operand:XF 0 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { + if (optimize_insn_for_size_p ()) + FAIL; emit_insn (gen_frndintxf2_floor (operands[0], operands[1])); DONE; }) @@ -17768,15 +17860,16 @@ "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size) + && flag_unsafe_math_optimizations) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !flag_trapping_math - && (TARGET_ROUND || !optimize_size))" + && !flag_trapping_math)" { if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && !flag_trapping_math - && (TARGET_ROUND || !optimize_size)) + && (TARGET_ROUND || optimize_insn_for_speed_p ())) { + if (!TARGET_ROUND && optimize_insn_for_size_p ()) + FAIL; if (TARGET_ROUND) emit_insn (gen_sse4_1_round2 (operands[0], operands[1], GEN_INT (0x01))); @@ -17787,9 +17880,13 @@ } else { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_frndintxf2_floor (op0, op1)); @@ -17960,9 +18057,10 @@ [(match_operand:DI 0 "nonimmediate_operand" "") (match_operand:MODEF 1 "register_operand" "")] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && TARGET_64BIT - && !flag_trapping_math - && !optimize_size" + && !flag_trapping_math" { + if (optimize_insn_for_size_p ()) + FAIL; ix86_expand_lfloorceil (operand0, operand1, true); DONE; }) @@ -17971,9 +18069,10 @@ [(match_operand:SI 0 "nonimmediate_operand" "") (match_operand:MODEF 1 "register_operand" "")] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !flag_trapping_math - && (!optimize_size || !TARGET_64BIT)" + && !flag_trapping_math" { + if (optimize_insn_for_size_p () && TARGET_64BIT) + FAIL; ix86_expand_lfloorceil (operand0, operand1, true); DONE; }) @@ -18021,8 +18120,10 @@ [(use (match_operand:XF 0 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { + if (optimize_insn_for_size_p ()) + FAIL; emit_insn (gen_frndintxf2_ceil (operands[0], operands[1])); DONE; }) @@ -18033,18 +18134,19 @@ "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size) + && flag_unsafe_math_optimizations) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !flag_trapping_math - && (TARGET_ROUND || !optimize_size))" + && !flag_trapping_math)" { if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && !flag_trapping_math - && (TARGET_ROUND || !optimize_size)) + && (TARGET_ROUND || optimize_insn_for_speed_p ())) { if (TARGET_ROUND) emit_insn (gen_sse4_1_round2 (operands[0], operands[1], GEN_INT (0x02))); + else if (optimize_insn_for_size_p ()) + FAIL; else if (TARGET_64BIT || (mode != DFmode)) ix86_expand_floorceil (operand0, operand1, false); else @@ -18052,9 +18154,13 @@ } else { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_frndintxf2_ceil (op0, op1)); @@ -18284,8 +18390,10 @@ [(use (match_operand:XF 0 "register_operand" "")) (use (match_operand:XF 1 "register_operand" ""))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations && !optimize_size" + && flag_unsafe_math_optimizations" { + if (optimize_insn_for_size_p ()) + FAIL; emit_insn (gen_frndintxf2_trunc (operands[0], operands[1])); DONE; }) @@ -18296,18 +18404,19 @@ "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations && !optimize_size) + && flag_unsafe_math_optimizations) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !flag_trapping_math - && (TARGET_ROUND || !optimize_size))" + && !flag_trapping_math)" { if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && !flag_trapping_math - && (TARGET_ROUND || !optimize_size)) + && (TARGET_ROUND || optimize_insn_for_speed_p ())) { if (TARGET_ROUND) emit_insn (gen_sse4_1_round2 (operands[0], operands[1], GEN_INT (0x03))); + else if (optimize_insn_for_size_p ()) + FAIL; else if (TARGET_64BIT || (mode != DFmode)) ix86_expand_trunc (operand0, operand1); else @@ -18315,9 +18424,13 @@ } else { - rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = gen_reg_rtx (XFmode); + rtx op0, op1; + + if (optimize_insn_for_size_p ()) + FAIL; + op0 = gen_reg_rtx (XFmode); + op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_frndintxf2_trunc (op0, op1)); @@ -18508,7 +18621,7 @@ operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust); /* Can't use this if the user has appropriated esi or edi. */ - if ((TARGET_SINGLE_STRINGOP || optimize_size) + if ((TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ()) && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])) { emit_insn (gen_strmov_singleop (operands[0], operands[1], @@ -18527,7 +18640,7 @@ (match_operand 4 "" "")) (set (match_operand 2 "register_operand" "") (match_operand 5 "" ""))])] - "TARGET_SINGLE_STRINGOP || optimize_size" + "" "ix86_current_function_needs_cld = 1;") (define_insn "*strmovdi_rex_1" @@ -18539,7 +18652,7 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 8)))] - "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "TARGET_64BIT && TARGET_SINGLE_STRINGOP" "movsq" [(set_attr "type" "str") (set_attr "mode" "DI") @@ -18554,7 +18667,7 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 4)))] - "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "!TARGET_64BIT && TARGET_SINGLE_STRINGOP" "movs{l|d}" [(set_attr "type" "str") (set_attr "mode" "SI") @@ -18569,7 +18682,7 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 4)))] - "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "TARGET_64BIT && TARGET_SINGLE_STRINGOP" "movs{l|d}" [(set_attr "type" "str") (set_attr "mode" "SI") @@ -18584,7 +18697,7 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 2)))] - "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "!TARGET_64BIT && TARGET_SINGLE_STRINGOP" "movsw" [(set_attr "type" "str") (set_attr "memory" "both") @@ -18599,7 +18712,7 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 2)))] - "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "TARGET_64BIT && TARGET_SINGLE_STRINGOP" "movsw" [(set_attr "type" "str") (set_attr "memory" "both") @@ -18614,7 +18727,7 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 1)))] - "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "!TARGET_64BIT && TARGET_SINGLE_STRINGOP" "movsb" [(set_attr "type" "str") (set_attr "memory" "both") @@ -18629,7 +18742,7 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 1)))] - "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "TARGET_64BIT && TARGET_SINGLE_STRINGOP" "movsb" [(set_attr "type" "str") (set_attr "memory" "both") @@ -18791,7 +18904,7 @@ operands[3] = gen_rtx_PLUS (Pmode, operands[0], GEN_INT (GET_MODE_SIZE (GET_MODE (operands[2])))); - if (TARGET_SINGLE_STRINGOP || optimize_size) + if (TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ()) { emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2], operands[3])); @@ -18804,7 +18917,7 @@ (match_operand 2 "register_operand" "")) (set (match_operand 0 "register_operand" "") (match_operand 3 "" ""))])] - "TARGET_SINGLE_STRINGOP || optimize_size" + "TARGET_SINGLE_STRINGOP" "ix86_current_function_needs_cld = 1;") (define_insn "*strsetdi_rex_1" @@ -18813,7 +18926,7 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 8)))] - "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "TARGET_64BIT && TARGET_SINGLE_STRINGOP" "stosq" [(set_attr "type" "str") (set_attr "memory" "store") @@ -18825,7 +18938,7 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 4)))] - "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "!TARGET_64BIT && TARGET_SINGLE_STRINGOP" "stos{l|d}" [(set_attr "type" "str") (set_attr "memory" "store") @@ -18837,7 +18950,7 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 4)))] - "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "TARGET_64BIT && TARGET_SINGLE_STRINGOP" "stos{l|d}" [(set_attr "type" "str") (set_attr "memory" "store") @@ -18849,7 +18962,7 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 2)))] - "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "!TARGET_64BIT && TARGET_SINGLE_STRINGOP" "stosw" [(set_attr "type" "str") (set_attr "memory" "store") @@ -18861,7 +18974,7 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 2)))] - "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "TARGET_64BIT && TARGET_SINGLE_STRINGOP" "stosw" [(set_attr "type" "str") (set_attr "memory" "store") @@ -18873,7 +18986,7 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 1)))] - "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "!TARGET_64BIT && TARGET_SINGLE_STRINGOP" "stosb" [(set_attr "type" "str") (set_attr "memory" "store") @@ -18885,7 +18998,7 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 1)))] - "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" + "TARGET_64BIT && TARGET_SINGLE_STRINGOP" "stosb" [(set_attr "type" "str") (set_attr "memory" "store") @@ -18990,10 +19103,13 @@ (match_operand:BLK 2 "general_operand" ""))) (use (match_operand 3 "general_operand" "")) (use (match_operand 4 "immediate_operand" ""))] - "! optimize_size || TARGET_INLINE_ALL_STRINGOPS" + "" { rtx addr1, addr2, out, outlow, count, countreg, align; + if (optimize_insn_for_size_p () && !TARGET_INLINE_ALL_STRINGOPS) + FAIL; + /* Can't use this if the user has appropriated esi or edi. */ if (fixed_regs[SI_REG] || fixed_regs[DI_REG]) FAIL; diff --git a/gcc/optabs.c b/gcc/optabs.c index 158e75999d88..5b27720dd8c4 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -3759,10 +3759,12 @@ expand_copysign (rtx op0, rtx op1, rtx target) with two operands: an output TARGET and an input OP0. TARGET *must* be nonzero, and the output is always stored there. CODE is an rtx code such that (CODE OP0) is an rtx that describes - the value that is stored into TARGET. */ + the value that is stored into TARGET. -void -emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) + Return false if expansion failed. */ + +bool +maybe_emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) { rtx temp; enum machine_mode mode0 = insn_data[icode].operand[1].mode; @@ -3779,6 +3781,8 @@ emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) temp = gen_reg_rtx (GET_MODE (temp)); pat = GEN_FCN (icode) (temp, op0); + if (!pat) + return false; if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) add_equal_note (pat, temp, code, op0, NULL_RTX); @@ -3787,6 +3791,19 @@ emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) if (temp != target) emit_move_insn (target, temp); + return true; +} +/* Generate an instruction whose insn-code is INSN_CODE, + with two operands: an output TARGET and an input OP0. + TARGET *must* be nonzero, and the output is always stored there. + CODE is an rtx code such that (CODE OP0) is an rtx that describes + the value that is stored into TARGET. */ + +void +emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) +{ + bool ok = maybe_emit_unop_insn (icode, target, op0, code); + gcc_assert (ok); } struct no_conflict_data @@ -5371,7 +5388,8 @@ expand_sfix_optab (rtx to, rtx from, convert_optab tab) if (imode != GET_MODE (to)) target = gen_reg_rtx (imode); - emit_unop_insn (icode, target, from, UNKNOWN); + if (!maybe_emit_unop_insn (icode, target, from, UNKNOWN)) + return false; if (target != to) convert_move (to, target, 0); return true; diff --git a/gcc/optabs.h b/gcc/optabs.h index 30a28d4816da..4d0ce5245ea3 100644 --- a/gcc/optabs.h +++ b/gcc/optabs.h @@ -722,6 +722,7 @@ extern rtx expand_copysign (rtx, rtx, rtx); /* Generate an instruction with a given INSN_CODE with an output and an input. */ extern void emit_unop_insn (int, rtx, rtx, enum rtx_code); +extern bool maybe_emit_unop_insn (int, rtx, rtx, enum rtx_code); /* Emit one rtl insn to compare two rtx's. */ extern void emit_cmp_insn (rtx, rtx, enum rtx_code, rtx, enum machine_mode,