From: Julian Seward Date: Mon, 1 Sep 2014 11:32:47 +0000 (+0000) Subject: Rename Iop_Extract{64,V128} to Iop_Slice{64,V128}, improve their X-Git-Tag: svn/VALGRIND_3_10_1^2~33 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=18d85d6308a3ee5bdc7c46fc994e402293bf6f9e;p=thirdparty%2Fvalgrind.git Rename Iop_Extract{64,V128} to Iop_Slice{64,V128}, improve their documentation, and swap the sense of the first and second args so as to be more in keeping with the rest of the ops here, so that the more significant arg is arg1 rather than arg2. git-svn-id: svn://svn.valgrind.org/vex/trunk@2939 --- diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index 6b2f2de56d..ab2bfe522b 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -2864,11 +2864,11 @@ Bool dis_neon_vext ( UInt theInstr, IRTemp condT ) HChar reg_t = Q ? 'q' : 'd'; if (Q) { - putQReg(dreg, triop(Iop_ExtractV128, getQReg(nreg), - getQReg(mreg), mkU8(imm4)), condT); + putQReg(dreg, triop(Iop_SliceV128, /*hiV128*/getQReg(mreg), + /*loV128*/getQReg(nreg), mkU8(imm4)), condT); } else { - putDRegI64(dreg, triop(Iop_Extract64, getDRegI64(nreg), - getDRegI64(mreg), mkU8(imm4)), condT); + putDRegI64(dreg, triop(Iop_Slice64, /*hiI64*/getDRegI64(mreg), + /*loI64*/getDRegI64(nreg), mkU8(imm4)), condT); } DIP("vext.8 %c%d, %c%d, %c%d, #%d\n", reg_t, dreg, reg_t, nreg, reg_t, mreg, imm4); diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c index 153f82851d..f1ac5aedf0 100644 --- a/VEX/priv/host_arm_isel.c +++ b/VEX/priv/host_arm_isel.c @@ -3710,10 +3710,10 @@ static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e ) IRTriop *triop = e->Iex.Triop.details; switch (triop->op) { - case Iop_Extract64: { + case Iop_Slice64: { HReg res = newVRegD(env); - HReg argL = iselNeon64Expr(env, triop->arg1); - HReg argR = iselNeon64Expr(env, triop->arg2); + HReg argL = iselNeon64Expr(env, triop->arg2); + HReg argR = iselNeon64Expr(env, triop->arg1); UInt imm4; if (triop->arg3->tag != Iex_Const || typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) { @@ -5291,10 +5291,10 @@ static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e ) IRTriop *triop = e->Iex.Triop.details; switch (triop->op) { - case Iop_ExtractV128: { + case Iop_SliceV128: { HReg res = newVRegV(env); - HReg argL = iselNeonExpr(env, triop->arg1); - HReg argR = iselNeonExpr(env, triop->arg2); + HReg argL = iselNeonExpr(env, triop->arg2); + HReg argR = iselNeonExpr(env, triop->arg1); UInt imm4; if (triop->arg3->tag != Iex_Const || typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) { diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index 55d24f0af6..5b840b9867 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -1041,8 +1041,8 @@ void ppIROp ( IROp op ) case Iop_SetElem16x4: vex_printf("SetElem16x4"); return; case Iop_SetElem32x2: vex_printf("SetElem32x2"); return; - case Iop_Extract64: vex_printf("Extract64"); return; - case Iop_ExtractV128: vex_printf("ExtractV128"); return; + case Iop_Slice64: vex_printf("Slice64"); return; + case Iop_SliceV128: vex_printf("SliceV128"); return; case Iop_Perm8x16: vex_printf("Perm8x16"); return; case Iop_Perm32x4: vex_printf("Perm32x4"); return; @@ -3075,9 +3075,9 @@ void typeOfPrimop ( IROp op, case Iop_SetElem32x2: TERNARY(Ity_I64, Ity_I8, Ity_I32, Ity_I64); - case Iop_Extract64: + case Iop_Slice64: TERNARY(Ity_I64, Ity_I64, Ity_I8, Ity_I64); - case Iop_ExtractV128: + case Iop_SliceV128: TERNARY(Ity_V128, Ity_V128, Ity_I8, Ity_V128); case Iop_BCDAdd: diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index f8cf781d25..a561278006 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -980,12 +980,12 @@ typedef /* DUPLICATING -- copy value to all lanes */ Iop_Dup8x8, Iop_Dup16x4, Iop_Dup32x2, - /* EXTRACT -- copy 8-arg3 highest bytes from arg1 to 8-arg3 lowest bytes - of result and arg3 lowest bytes of arg2 to arg3 highest bytes of - result. - It is a triop: (I64, I64, I8) -> I64 */ - /* Note: the arm back-end handles only constant third argumnet. */ - Iop_Extract64, + /* SLICE -- produces the lowest 64 bits of (arg1:arg2) >> (8 * arg3). + arg3 is a shift amount in bytes and may be between 0 and 8 + inclusive. When 0, the result is arg2; when 8, the result is arg1. + Not all back ends handle all values. The arm32 and arm64 back + ends handle only immediate arg3 values. */ + Iop_Slice64, // (I64, I64, I8) -> I64 /* REVERSE the order of chunks in vector lanes. Chunks must be smaller than the vector lanes (obviously) and so may be 8-, @@ -1711,12 +1711,12 @@ typedef /* DUPLICATING -- copy value to all lanes */ Iop_Dup8x16, Iop_Dup16x8, Iop_Dup32x4, - /* EXTRACT -- copy 16-arg3 highest bytes from arg1 to 16-arg3 lowest bytes - of result and arg3 lowest bytes of arg2 to arg3 highest bytes of - result. - It is a triop: (V128, V128, I8) -> V128 */ - /* Note: the ARM back end handles only constant arg3 in this operation. */ - Iop_ExtractV128, + /* SLICE -- produces the lowest 128 bits of (arg1:arg2) >> (8 * arg3). + arg3 is a shift amount in bytes and may be between 0 and 16 + inclusive. When 0, the result is arg2; when 16, the result is arg1. + Not all back ends handle all values. The arm64 back + end handles only immediate arg3 values. */ + Iop_SliceV128, // (V128, V128, I8) -> V128 /* REVERSE the order of chunks in vector lanes. Chunks must be smaller than the vector lanes (obviously) and so may be 8-,