From: Petar Jovanovic <mips32r2@gmail.com>
Date: Tue, 31 Dec 2019 15:56:23 +0000 (+0000)
Subject: mips: update tests to compile for nanoMIPS
X-Git-Tag: VALGRIND_3_16_0~175
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=192c1673c75737c9ea6b5af7cfdc7b0681759933;p=thirdparty%2Fvalgrind.git

mips: update tests to compile for nanoMIPS

Update the tests so they can be compiled for nanoMIPS.

Patch by Dimitrije Nikolic and Aleksandra Karadzic.
---

diff --git a/helgrind/tests/tc07_hbl1.c b/helgrind/tests/tc07_hbl1.c
index 1744dc1304..3972b512ee 100644
--- a/helgrind/tests/tc07_hbl1.c
+++ b/helgrind/tests/tc07_hbl1.c
@@ -39,6 +39,8 @@
 #  define PLAT_s390x_linux 1
 #elif defined(__linux__) && defined(__mips__)
 #  define PLAT_mips32_linux 1
+#elif defined(__linux__) && defined(__nanomips__)
+#  define PLAT_nanomips_linux 1
 #elif defined(__sun__) && defined(__i386__)
 #  define PLAT_x86_solaris 1
 #elif defined(__sun__) && defined(__x86_64__)
@@ -110,6 +112,18 @@
       : /*out*/ : /*in*/ "r"(&(_lval))              \
       : /*trash*/ "$8", "$9", "$10", "cc", "memory" \
    )
+#elif defined(PLAT_nanomips_linux)
+#  define INC(_lval,_lqual)                         \
+     __asm__ __volatile__ (                         \
+      "1:\n"                                        \
+      "        move $t0, %0\n"                      \
+      "        ll $t1, 0($t0)\n"                    \
+      "        addiu $t1, $t1, 1\n"                 \
+      "        sc $t1, 0($t0)\n"                    \
+      "        beqc $t1, $zero, 1b\n"               \
+      : /*out*/ : /*in*/ "r"(&(_lval))              \
+      : /*trash*/ "$t0", "$t1", "memory"            \
+   )
 #else
 #  error "Fix Me for this platform"
 #endif
diff --git a/helgrind/tests/tc08_hbl2.c b/helgrind/tests/tc08_hbl2.c
index f660d82dd9..e84ecec4a1 100644
--- a/helgrind/tests/tc08_hbl2.c
+++ b/helgrind/tests/tc08_hbl2.c
@@ -60,6 +60,8 @@
 #else
 #  define PLAT_mips32_linux 1
 #endif
+#elif defined(__linux__) && defined(__nanomips__)
+#  define PLAT_nanomips_linux 1
 #elif defined(__sun__) && defined(__i386__)
 #  define PLAT_x86_solaris 1
 #elif defined(__sun__) && defined(__x86_64__)
@@ -130,6 +132,18 @@
       : /*out*/ : /*in*/ "r"(&(_lval))              \
       : /*trash*/ "t0", "t1", "memory"              \
         )
+#elif defined(PLAT_nanomips_linux)
+#  define INC(_lval,_lqual)                         \
+     __asm__ __volatile__ (                         \
+      "1:\n"                                        \
+      "        move $t0, %0\n"                      \
+      "        ll $t1, 0($t0)\n"                    \
+      "        addiu $t1, $t1, 1\n"                 \
+      "        sc $t1, 0($t0)\n"                    \
+      "        beqc $t1, $zero, 1b\n"               \
+      : /*out*/ : /*in*/ "r"(&(_lval))              \
+      : /*trash*/ "$t0", "$t1", "memory"            \
+   )
 #else
 #  error "Fix Me for this platform"
 #endif
diff --git a/helgrind/tests/tc11_XCHG.c b/helgrind/tests/tc11_XCHG.c
index 48fc1b1a9e..15167e87e8 100644
--- a/helgrind/tests/tc11_XCHG.c
+++ b/helgrind/tests/tc11_XCHG.c
@@ -41,6 +41,8 @@
 #  define PLAT_s390x_linux 1
 #elif defined(__linux__) && defined(__mips__)
 #  define PLAT_mips32_linux 1
+#elif defined(__linux__) && defined(__nanomips__)
+#  define PLAT_nanomips_linux 1
 #elif defined(__sun__) && defined(__i386__)
 #  define PLAT_x86_solaris 1
 #elif defined(__sun__) && defined(__x86_64__)
@@ -96,6 +98,21 @@
         : "$12", "$13", "$14", "memory", "cc"                \
      )
 
+#  define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \
+      XCHG_M_R(_addr,_lval)
+#elif defined(PLAT_nanomips_linux)
+#  define XCHG_M_R(_addr,_lval)                              \
+     __asm__ __volatile__(                                   \
+        "move $t0, %2\n"                                     \
+        "move $t1, %1\n"                                     \
+        "ll $t2, 0($t1)\n"                                   \
+        "sc $t0, 0($t1)\n"                                   \
+        "move %0, $t2\n"                                     \
+        : /*out*/ "=r"(_lval)                                \
+        : /*in*/  "r"(&_addr), "r"(_lval)                    \
+        : "$t0", "$t1", "$t1", "memory"                      \
+     )
+
 #  define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \
       XCHG_M_R(_addr,_lval)
 
diff --git a/memcheck/tests/atomic_incs.c b/memcheck/tests/atomic_incs.c
index b6816d78a7..f931750f47 100644
--- a/memcheck/tests/atomic_incs.c
+++ b/memcheck/tests/atomic_incs.c
@@ -146,7 +146,7 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n )
       : "+m" (*p), "+m" (dummy)
       : "d" (n)
       : "cc", "memory", "0", "1");
-#elif defined(VGA_mips32)
+#elif defined(VGA_mips32) || defined (VGA_nanomips)
    /* We rely on the fact that p is 4-aligned. Otherwise 'll' may throw an
       exception that can cause this function to fail. */
 #if defined (_MIPSEL)
@@ -362,7 +362,7 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n )
       : "+m" (*p), "+m" (dummy)
       : "d" (n)
       : "cc", "memory", "0", "1");
-#elif defined(VGA_mips32)
+#elif defined(VGA_mips32) || defined (VGA_nanomips)
    /* We rely on the fact that p is 4-aligned. Otherwise 'll' may throw an
       exception that can cause this function to fail. */
 #if defined (_MIPSEL)
@@ -571,7 +571,7 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n )
       : "+m" (*p)
       : "d" (n)
       : "cc", "memory", "0", "1");
-#elif defined(VGA_mips32)
+#elif defined(VGA_mips32) || defined (VGA_nanomips)
    unsigned int block[3]
       = { (unsigned int)p, (unsigned int)n, 0x0 };
    do {
@@ -612,7 +612,8 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n )
 
 __attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n ) 
 {
-#if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_mips32)
+#if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_mips32) \
+ || defined (VGA_nanomips)
    /* do nothing; is not supported */
 #elif defined(VGA_amd64)
    // this is a bit subtle.  It relies on the fact that, on a 64-bit platform,
diff --git a/memcheck/tests/leak.h b/memcheck/tests/leak.h
index a1f93e8aaa..9056cf0971 100644
--- a/memcheck/tests/leak.h
+++ b/memcheck/tests/leak.h
@@ -60,6 +60,33 @@
    __asm__ __volatile__( "li 11, 0" : : :/*trash*/"r11" ); \
    __asm__ __volatile__( "li 12, 0" : : :/*trash*/"r12" ); \
   } while (0)
+#elif defined(__nanomips__)
+#define CLEAR_CALLER_SAVED_REGS                                             \
+   do {                                                                     \
+      __asm__ __volatile__ (".set push       \n\t"                          \
+                            ".set noat       \n\t"                          \
+                            "move $at, $zero \n\t"                          \
+                            "move $t4, $zero \n\t"                          \
+                            "move $t5, $zero \n\t"                          \
+                            "move $a0, $zero \n\t"                          \
+                            "move $a1, $zero \n\t"                          \
+                            "move $a2, $zero \n\t"                          \
+                            "move $a3, $zero \n\t"                          \
+                            "move $a4, $zero \n\t"                          \
+                            "move $a5, $zero \n\t"                          \
+                            "move $a6, $zero \n\t"                          \
+                            "move $a7, $zero \n\t"                          \
+                            "move $t0, $zero \n\t"                          \
+                            "move $t1, $zero \n\t"                          \
+                            "move $t2, $zero \n\t"                          \
+                            "move $t3, $zero \n\t"                          \
+                            "move $t8, $zero \n\t"                          \
+                            "move $t9, $zero \n\t"                          \
+                            ".set pop        \n\t"                          \
+                            : : : "$at", "$t4", "$t5", "$a0", "$a1", "$a2", \
+                                  "$a3", "$a4", "$a5", "$a6", "$a7", "$t0", \
+                                  "$t1", "$t2", "$t3", "$t8", "$t9");       \
+   } while (0)
 #elif (__mips == 32)
 #define CLEAR_CALLER_SAVED_REGS                                              \
    do {                                                                      \
diff --git a/memcheck/tests/unit_libcbase.c b/memcheck/tests/unit_libcbase.c
index 2944cea725..0ce65be264 100644
--- a/memcheck/tests/unit_libcbase.c
+++ b/memcheck/tests/unit_libcbase.c
@@ -15,7 +15,8 @@
 unsigned long VKI_PAGE_SIZE  = 1UL << 12;
 #elif defined(VGP_arm64_linux)
 unsigned long VKI_PAGE_SIZE  = 1UL << 16;
-#elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
+#elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
+    || defined (VGP_nanomips_linux)
 #include <unistd.h>
 unsigned long VKI_PAGE_SIZE;
 #endif
diff --git a/none/tests/libvex_test.c b/none/tests/libvex_test.c
index bb1738a0b1..5b57a4c2e2 100644
--- a/none/tests/libvex_test.c
+++ b/none/tests/libvex_test.c
@@ -74,6 +74,8 @@ __attribute__((noinline)) static void get_guest_arch(VexArch    *ga)
    *ga = VexArchMIPS32;
 #elif defined(VGA_mips64)
    *ga = VexArchMIPS64;
+#elif defined(VGA_nanomips)
+   *ga = VexArchNANOMIPS;
 #else
    missing arch;
 #endif
@@ -94,6 +96,7 @@ static VexEndness arch_endness (VexArch va) {
    case VexArchS390X:  return VexEndnessBE;
    case VexArchMIPS32:
    case VexArchMIPS64:
+   case VexArchNANOMIPS:
       /* mips32/64 supports BE or LE, but at compile time.
          If mips64 is compiled on a non mips system, the VEX lib
          is missing bit and pieces of code related to endianness.
@@ -105,7 +108,7 @@ static VexEndness arch_endness (VexArch va) {
          VexArch ga;
          get_guest_arch( &ga);
 
-         if (ga == VexArchMIPS64 || ga == VexArchMIPS32)
+         if (ga == VexArchMIPS64 || ga == VexArchMIPS32 || ga == VexArchNANOMIPS)
             return running_endness();
          else
             return VexEndnessBE;
@@ -135,6 +138,7 @@ static UInt arch_hwcaps (VexArch va) {
    case VexArchMIPS32: return VEX_PRID_COMP_MIPS;
    case VexArchMIPS64: return VEX_PRID_COMP_MIPS | VEX_MIPS_HOST_FR;
 #endif
+   case VexArchNANOMIPS: return 0;
    default: failure_exit();
    }
 }
@@ -151,6 +155,7 @@ static Bool mode64 (VexArch va) {
    case VexArchS390X:  return True;
    case VexArchMIPS32: return False;
    case VexArchMIPS64: return True;
+   case VexArchNANOMIPS: return False;
    default: failure_exit();
    }
 }
@@ -270,7 +275,7 @@ int main(int argc, char **argv)
    // explicitly via command line arguments.
    if (multiarch) {
       VexArch va;
-      for (va = VexArchX86; va <= VexArchMIPS64; va++) {
+      for (va = VexArchX86; va <= VexArchNANOMIPS; va++) {
          vta.arch_host = va;
          vta.archinfo_host.endness = arch_endness (vta.arch_host);
          vta.archinfo_host.hwcaps = arch_hwcaps (vta.arch_host);
diff --git a/perf/bigcode.c b/perf/bigcode.c
index 02e069d9f6..e2adf0ec46 100644
--- a/perf/bigcode.c
+++ b/perf/bigcode.c
@@ -85,6 +85,8 @@ int main(int argc, char* argv[])
 
 #if defined(__mips__)
    syscall(__NR_cacheflush, a, FN_SIZE * n_fns, ICACHE);
+#elif defined(__nanomips__)
+   __builtin___clear_cache(a, (char*)a + FN_SIZE * n_fns);
 #endif
 
    for (h = 0; h < n_reps; h += 1) {