From: Jeff Law <jeffreyalaw@gmail.com>
Date: Mon, 17 Oct 2022 23:42:27 +0000 (-0400)
Subject: More infrastructure to avoid bogus RTL on H8.
X-Git-Tag: basepoints/gcc-14~3860
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=19859bd72119708c85cc6976b3547738be6f5b1c;p=thirdparty%2Fgcc.git

More infrastructure to avoid bogus RTL on H8.

Continuing the work to add constraints to avoid invalid RTL
with autoinc addressing modes.  Specifically this patch adds
the memory constraints similar to the pdp11.

gcc/

	* config/h8300/constraints.md (Za..Zh): New constraints for
	autoinc addresses using a specific register.
	* config/h8300/h8300.cc (pre_incdec_with_reg): New function.
	* config/h8300/h8300-protos.h (pre_incdec_with_reg): Add prototype.
---

diff --git a/gcc/config/h8300/constraints.md b/gcc/config/h8300/constraints.md
index 6eaffc169759..7e6681c44921 100644
--- a/gcc/config/h8300/constraints.md
+++ b/gcc/config/h8300/constraints.md
@@ -241,3 +241,11 @@
 (define_register_constraint "Z7" "NOT_SP_REGS"
   "@internal")
 
+(define_constraint "Za" "@internal" (match_test "pre_incdec_with_reg (op, 0)"))
+(define_constraint "Zb" "@internal" (match_test "pre_incdec_with_reg (op, 1)"))
+(define_constraint "Zc" "@internal" (match_test "pre_incdec_with_reg (op, 2)"))
+(define_constraint "Zd" "@internal" (match_test "pre_incdec_with_reg (op, 3)"))
+(define_constraint "Ze" "@internal" (match_test "pre_incdec_with_reg (op, 4)"))
+(define_constraint "Zf" "@internal" (match_test "pre_incdec_with_reg (op, 5)"))
+(define_constraint "Zg" "@internal" (match_test "pre_incdec_with_reg (op, 6)"))
+(define_constraint "Zh" "@internal" (match_test "pre_incdec_with_reg (op, 7)"))
diff --git a/gcc/config/h8300/h8300-protos.h b/gcc/config/h8300/h8300-protos.h
index e9d434c0d5a0..8c989495c293 100644
--- a/gcc/config/h8300/h8300-protos.h
+++ b/gcc/config/h8300/h8300-protos.h
@@ -100,6 +100,7 @@ extern int h8300_initial_elimination_offset (int, int);
 extern int h8300_regs_ok_for_stm (int, rtx[]);
 extern int h8300_hard_regno_rename_ok (unsigned int, unsigned int);
 extern bool h8300_move_ok (rtx, rtx);
+extern bool pre_incdec_with_reg (rtx, int);
 
 struct cpp_reader;
 extern void h8300_pr_interrupt (struct cpp_reader *);
diff --git a/gcc/config/h8300/h8300.cc b/gcc/config/h8300/h8300.cc
index be3e385c91e9..ce0702edecb0 100644
--- a/gcc/config/h8300/h8300.cc
+++ b/gcc/config/h8300/h8300.cc
@@ -5531,6 +5531,32 @@ h8300_ok_for_sibcall_p (tree fndecl, tree)
 
   return 1;
 }
+
+/* Return TRUE if OP is a PRE_INC or PRE_DEC
+   instruction using REG, FALSE otherwise.  */
+
+bool
+pre_incdec_with_reg (rtx op, int reg)
+{
+  /* OP must be a MEM.  */
+  if (GET_CODE (op) != MEM)
+    return false;
+
+  /* The address must be a PRE_INC or PRE_DEC.  */
+  op = XEXP (op, 0);
+  if (GET_CODE (op) != PRE_DEC && GET_CODE (op) != PRE_INC)
+    return false;
+
+  /* It must be a register that is being incremented
+     or decremented.  */
+  op = XEXP (op, 0);
+  if (!REG_P (op))
+    return false;
+
+  /* Finally, check that the register number matches.  */
+  return REGNO (op) == reg;
+}
+
 
 /* Initialize the GCC target structure.  */
 #undef TARGET_ATTRIBUTE_TABLE