From: Geert Uytterhoeven Date: Fri, 16 May 2025 13:32:18 +0000 (+0200) Subject: spi: sh-msiof: Correct RX FIFO size for R-Car Gen2 X-Git-Tag: v6.16-rc1~166^2~8^2~6 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1ab2c8c45f5c5df6707cc848686e674f4ec5c3d9;p=thirdparty%2Fkernel%2Fstable.git spi: sh-msiof: Correct RX FIFO size for R-Car Gen2 According to Renesas Technical Updates TN-RCS-S068A/E, the MSIOF receive FIFOs on R-Car Gen2 SoCs have room for 128 words of 32 bits. Note that this change has no actual impact on the behavior of the driver, as SPI_CONTROLLER_MUST_TX is set, and transfer size is currenty limited to the minimum of the transmit and receive FIFO sizes. Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/fd11933f932df81d84f417a21e2179bd4fdcfdc1.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index ea9277ab87f66..8d18a26128d60 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -1099,7 +1099,7 @@ static const struct sh_msiof_chipdata rcar_gen2_data = { .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(24) | SPI_BPW_MASK(32), .tx_fifo_size = 64, - .rx_fifo_size = 64, + .rx_fifo_size = 128, .ctlr_flags = SPI_CONTROLLER_MUST_TX, .min_div_pow = 0, };