From: H.J. Lu Date: Mon, 21 May 2018 17:54:20 +0000 (-0700) Subject: Initial Fast Short REP MOVSB (FSRM) support X-Git-Tag: glibc-2.28~264 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1af30adcd59fae929371d3a56b239861b1088a6e;p=thirdparty%2Fglibc.git Initial Fast Short REP MOVSB (FSRM) support The newer Intel processors support Fast Short REP MOVSB which has a feature bit in CPUID. This patch adds the Fast Short REP MOVSB (FSRM) bit to x86 cpu-features. * sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New. (index_cpu_FSRM): Likewise. (reg_FSRM): Likewise. --- diff --git a/ChangeLog b/ChangeLog index 6e9b14cffee..c8ff9d45c83 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2018-05-21 H.J. Lu + + * sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New. + (index_cpu_FSRM): Likewise. + (reg_FSRM): Likewise. + 2018-05-18 Joseph Myers * math/gen-tgmath-tests.py: Import sys. diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index c60c2e4eeb8..2088bd73eef 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -76,6 +76,7 @@ #define bit_cpu_AVX512VL (1u << 31) #define bit_cpu_IBT (1u << 20) #define bit_cpu_SHSTK (1u << 7) +#define bit_cpu_FSRM (1 << 4) /* XCR0 Feature flags. */ #define bit_XMM_state (1 << 1) @@ -207,6 +208,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_cpu_POPCNT COMMON_CPUID_INDEX_1 # define index_cpu_IBT COMMON_CPUID_INDEX_7 # define index_cpu_SHSTK COMMON_CPUID_INDEX_7 +# define index_cpu_FSRM COMMON_CPUID_INDEX_7 # define reg_CX8 edx # define reg_CMOV edx @@ -238,6 +240,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define reg_POPCNT ecx # define reg_IBT edx # define reg_SHSTK ecx +# define reg_FSRM edx # define index_arch_Fast_Rep_String FEATURE_INDEX_1 # define index_arch_Fast_Copy_Backward FEATURE_INDEX_1