From: Pan Li <pan2.li@intel.com>
Date: Wed, 16 Aug 2023 07:55:42 +0000 (+0800)
Subject: RISC-V: Support RVV VFWCVT.XU.F.V rounding mode intrinsic API
X-Git-Tag: basepoints/gcc-15~6897
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1b7418ba1baf0d43fff6c6a68b8134813a35c1d9;p=thirdparty%2Fgcc.git

RISC-V: Support RVV VFWCVT.XU.F.V rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.

* __riscv_vfwcvt_xu_f_v_u64m2_rm
* __riscv_vfwcvt_xu_f_v_u64m2_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(BASE): New declaration.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfwcvt_xu_frm): New intrinsic function def.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-wcvt-xu.c: New test.
---

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 18453e54b519..050ecbe780c9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2497,6 +2497,7 @@ static CONSTEXPR const vfcvt_f<HAS_FRM> vfcvt_f_frm_obj;
 static CONSTEXPR const vfwcvt_x<UNSPEC_VFCVT> vfwcvt_x_obj;
 static CONSTEXPR const vfwcvt_x<UNSPEC_VFCVT, HAS_FRM> vfwcvt_x_frm_obj;
 static CONSTEXPR const vfwcvt_x<UNSPEC_UNSIGNED_VFCVT> vfwcvt_xu_obj;
+static CONSTEXPR const vfwcvt_x<UNSPEC_UNSIGNED_VFCVT, HAS_FRM> vfwcvt_xu_frm_obj;
 static CONSTEXPR const vfwcvt_rtz_x<FIX> vfwcvt_rtz_x_obj;
 static CONSTEXPR const vfwcvt_rtz_x<UNSIGNED_FIX> vfwcvt_rtz_xu_obj;
 static CONSTEXPR const vfwcvt_f vfwcvt_f_obj;
@@ -2750,6 +2751,7 @@ BASE (vfcvt_f_frm)
 BASE (vfwcvt_x)
 BASE (vfwcvt_x_frm)
 BASE (vfwcvt_xu)
+BASE (vfwcvt_xu_frm)
 BASE (vfwcvt_rtz_x)
 BASE (vfwcvt_rtz_xu)
 BASE (vfwcvt_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index dd711846cbe4..6565740c5977 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -215,6 +215,7 @@ extern const function_base *const vfcvt_f_frm;
 extern const function_base *const vfwcvt_x;
 extern const function_base *const vfwcvt_x_frm;
 extern const function_base *const vfwcvt_xu;
+extern const function_base *const vfwcvt_xu_frm;
 extern const function_base *const vfwcvt_rtz_x;
 extern const function_base *const vfwcvt_rtz_xu;
 extern const function_base *const vfwcvt_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 4e6cc793447e..22c039c8cbb9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -460,6 +460,7 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, u_to_wf_xu_v_ops)
 DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, f_to_wf_f_v_ops)
 
 DEF_RVV_FUNCTION (vfwcvt_x_frm, alu_frm, full_preds, f_to_wi_f_v_ops)
+DEF_RVV_FUNCTION (vfwcvt_xu_frm, alu_frm, full_preds, f_to_wu_f_v_ops)
 
 // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
 DEF_RVV_FUNCTION (vfncvt_x, narrow_alu, full_preds, f_to_ni_f_w_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
new file mode 100644
index 000000000000..29449e79b69f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vuint64m2_t
+test_riscv_vfwcvt_xu_f_v_u64m2_rm (vfloat32m1_t op1, size_t vl) {
+  return __riscv_vfwcvt_xu_f_v_u64m2_rm (op1, 0, vl);
+}
+
+vuint64m2_t
+test_vfwcvt_xu_f_v_u64m2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+  return __riscv_vfwcvt_xu_f_v_u64m2_rm_m (mask, op1, 1, vl);
+}
+
+vuint64m2_t
+test_riscv_vfwcvt_xu_f_v_u64m2 (vfloat32m1_t op1, size_t vl) {
+  return __riscv_vfwcvt_xu_f_v_u64m2 (op1, vl);
+}
+
+vuint64m2_t
+test_vfwcvt_xu_f_v_u64m2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+  return __riscv_vfwcvt_xu_f_v_u64m2_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */