From: Sasha Levin Date: Sat, 14 Jan 2023 14:23:24 +0000 (-0500) Subject: Fixes for 6.0 X-Git-Tag: v4.14.303~63^2~4 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1b8d376afbcbeb78bf1532182bf6b482f134a5b6;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.0 Signed-off-by: Sasha Levin --- diff --git a/queue-6.0/ata-ahci-fix-enum-constants-for-gcc-13.patch b/queue-6.0/ata-ahci-fix-enum-constants-for-gcc-13.patch new file mode 100644 index 00000000000..6853481f112 --- /dev/null +++ b/queue-6.0/ata-ahci-fix-enum-constants-for-gcc-13.patch @@ -0,0 +1,370 @@ +From 3a2ee178170a1d7d329913e74eabdfbb56efb7a4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 3 Dec 2022 11:54:25 +0100 +Subject: ata: ahci: fix enum constants for gcc-13 + +From: Arnd Bergmann + +[ Upstream commit f07788079f515ca4a681c5f595bdad19cfbd7b1d ] + +gcc-13 slightly changes the type of constant expressions that are defined +in an enum, which triggers a compile time sanity check in libata: + +linux/drivers/ata/libahci.c: In function 'ahci_led_store': +linux/include/linux/compiler_types.h:357:45: error: call to '__compiletime_assert_302' declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long) +357 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) + +The new behavior is that sizeof() returns the same value for the +constant as it does for the enum type, which is generally more sensible +and consistent. + +The problem in libata is that it contains a single enum definition for +lots of unrelated constants, some of which are large positive (unsigned) +integers like 0xffffffff, while others like (1<<31) are interpreted as +negative integers, and this forces the enum type to become 64 bit wide +even though most constants would still fit into a signed 32-bit 'int'. + +Fix this by changing the entire enum definition to use BIT(x) in place +of (1< +Cc: linux-ide@vger.kernel.org +Cc: Damien Le Moal +Cc: stable@vger.kernel.org +Cc: Randy Dunlap +Signed-off-by: Arnd Bergmann +Tested-by: Luis Machado +Signed-off-by: Damien Le Moal +Signed-off-by: Sasha Levin +--- + drivers/ata/ahci.h | 245 +++++++++++++++++++++++---------------------- + 1 file changed, 123 insertions(+), 122 deletions(-) + +diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h +index 60bbea86919c..8ec542ba28e0 100644 +--- a/drivers/ata/ahci.h ++++ b/drivers/ata/ahci.h +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + /* Enclosure Management Control */ + #define EM_CTRL_MSG_TYPE 0x000f0000 +@@ -54,12 +55,12 @@ enum { + AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + + AHCI_CMD_TBL_AR_SZ + + (AHCI_RX_FIS_SZ * 16), +- AHCI_IRQ_ON_SG = (1 << 31), +- AHCI_CMD_ATAPI = (1 << 5), +- AHCI_CMD_WRITE = (1 << 6), +- AHCI_CMD_PREFETCH = (1 << 7), +- AHCI_CMD_RESET = (1 << 8), +- AHCI_CMD_CLR_BUSY = (1 << 10), ++ AHCI_IRQ_ON_SG = BIT(31), ++ AHCI_CMD_ATAPI = BIT(5), ++ AHCI_CMD_WRITE = BIT(6), ++ AHCI_CMD_PREFETCH = BIT(7), ++ AHCI_CMD_RESET = BIT(8), ++ AHCI_CMD_CLR_BUSY = BIT(10), + + RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ + RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ +@@ -77,37 +78,37 @@ enum { + HOST_CAP2 = 0x24, /* host capabilities, extended */ + + /* HOST_CTL bits */ +- HOST_RESET = (1 << 0), /* reset controller; self-clear */ +- HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ +- HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ +- HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ ++ HOST_RESET = BIT(0), /* reset controller; self-clear */ ++ HOST_IRQ_EN = BIT(1), /* global IRQ enable */ ++ HOST_MRSM = BIT(2), /* MSI Revert to Single Message */ ++ HOST_AHCI_EN = BIT(31), /* AHCI enabled */ + + /* HOST_CAP bits */ +- HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ +- HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ +- HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ +- HOST_CAP_PART = (1 << 13), /* Partial state capable */ +- HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ +- HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ +- HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ +- HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ +- HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ +- HOST_CAP_CLO = (1 << 24), /* Command List Override support */ +- HOST_CAP_LED = (1 << 25), /* Supports activity LED */ +- HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ +- HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ +- HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ +- HOST_CAP_SNTF = (1 << 29), /* SNotification register */ +- HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ +- HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ ++ HOST_CAP_SXS = BIT(5), /* Supports External SATA */ ++ HOST_CAP_EMS = BIT(6), /* Enclosure Management support */ ++ HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */ ++ HOST_CAP_PART = BIT(13), /* Partial state capable */ ++ HOST_CAP_SSC = BIT(14), /* Slumber state capable */ ++ HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */ ++ HOST_CAP_FBS = BIT(16), /* FIS-based switching support */ ++ HOST_CAP_PMP = BIT(17), /* Port Multiplier support */ ++ HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */ ++ HOST_CAP_CLO = BIT(24), /* Command List Override support */ ++ HOST_CAP_LED = BIT(25), /* Supports activity LED */ ++ HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */ ++ HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */ ++ HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */ ++ HOST_CAP_SNTF = BIT(29), /* SNotification register */ ++ HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */ ++ HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */ + + /* HOST_CAP2 bits */ +- HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ +- HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ +- HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ +- HOST_CAP2_SDS = (1 << 3), /* Support device sleep */ +- HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */ +- HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */ ++ HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */ ++ HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */ ++ HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */ ++ HOST_CAP2_SDS = BIT(3), /* Support device sleep */ ++ HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */ ++ HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */ + + /* registers for each SATA port */ + PORT_LST_ADDR = 0x00, /* command list DMA addr */ +@@ -129,24 +130,24 @@ enum { + PORT_DEVSLP = 0x44, /* device sleep */ + + /* PORT_IRQ_{STAT,MASK} bits */ +- PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ +- PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ +- PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ +- PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ +- PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ +- PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ +- PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ +- PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ +- +- PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ +- PORT_IRQ_DMPS = (1 << 7), /* mechanical presence status */ +- PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ +- PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ +- PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ +- PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ +- PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ +- PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ +- PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ ++ PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */ ++ PORT_IRQ_TF_ERR = BIT(30), /* task file error */ ++ PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */ ++ PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */ ++ PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */ ++ PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */ ++ PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */ ++ PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */ ++ ++ PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */ ++ PORT_IRQ_DMPS = BIT(7), /* mechanical presence status */ ++ PORT_IRQ_CONNECT = BIT(6), /* port connect change status */ ++ PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */ ++ PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */ ++ PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */ ++ PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */ ++ PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */ ++ PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */ + + PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | + PORT_IRQ_IF_ERR | +@@ -162,27 +163,27 @@ enum { + PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, + + /* PORT_CMD bits */ +- PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ +- PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ +- PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ +- PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ +- PORT_CMD_ESP = (1 << 21), /* External Sata Port */ +- PORT_CMD_CPD = (1 << 20), /* Cold Presence Detection */ +- PORT_CMD_MPSP = (1 << 19), /* Mechanical Presence Switch */ +- PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ +- PORT_CMD_PMP = (1 << 17), /* PMP attached */ +- PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ +- PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ +- PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ +- PORT_CMD_CLO = (1 << 3), /* Command list override */ +- PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ +- PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ +- PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ +- +- PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ +- PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ +- PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ +- PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ ++ PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */ ++ PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */ ++ PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */ ++ PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */ ++ PORT_CMD_ESP = BIT(21), /* External Sata Port */ ++ PORT_CMD_CPD = BIT(20), /* Cold Presence Detection */ ++ PORT_CMD_MPSP = BIT(19), /* Mechanical Presence Switch */ ++ PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */ ++ PORT_CMD_PMP = BIT(17), /* PMP attached */ ++ PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */ ++ PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */ ++ PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */ ++ PORT_CMD_CLO = BIT(3), /* Command list override */ ++ PORT_CMD_POWER_ON = BIT(2), /* Power up device */ ++ PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */ ++ PORT_CMD_START = BIT(0), /* Enable port DMA engine */ ++ ++ PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */ ++ PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */ ++ PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */ ++ PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */ + + /* PORT_CMD capabilities mask */ + PORT_CMD_CAP = PORT_CMD_HPCP | PORT_CMD_MPSP | +@@ -193,9 +194,9 @@ enum { + PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ + PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ + PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ +- PORT_FBS_SDE = (1 << 2), /* FBS single device error */ +- PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ +- PORT_FBS_EN = (1 << 0), /* Enable FBS */ ++ PORT_FBS_SDE = BIT(2), /* FBS single device error */ ++ PORT_FBS_DEC = BIT(1), /* FBS device error clear */ ++ PORT_FBS_EN = BIT(0), /* Enable FBS */ + + /* PORT_DEVSLP bits */ + PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ +@@ -203,50 +204,50 @@ enum { + PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ + PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ + PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ +- PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */ +- PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */ ++ PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */ ++ PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */ + + /* hpriv->flags bits */ + + #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) + +- AHCI_HFLAG_NO_NCQ = (1 << 0), +- AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ +- AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ +- AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ +- AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ +- AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ +- AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ +- AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ +- AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ +- AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ +- AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as +- link offline */ +- AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ +- AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ +- AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ +- AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on +- port start (wait until +- error-handling stage) */ +- AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */ +- AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ ++ AHCI_HFLAG_NO_NCQ = BIT(0), ++ AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */ ++ AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */ ++ AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */ ++ AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */ ++ AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */ ++ AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */ ++ AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */ ++ AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */ ++ AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */ ++ AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as ++ link offline */ ++ AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */ ++ AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */ ++ AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */ ++ AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on ++ port start (wait until ++ error-handling stage) */ ++ AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */ ++ AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */ + + #ifdef CONFIG_PCI_MSI +- AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */ ++ AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */ + #else + /* compile out MSI infrastructure */ + AHCI_HFLAG_MULTI_MSI = 0, + #endif +- AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */ +- AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */ +- AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read +- only registers */ +- AHCI_HFLAG_USE_LPM_POLICY = (1 << 25), /* chipset that should use +- SATA_MOBILE_LPM_POLICY +- as default lpm_policy */ +- AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during +- suspend/resume */ +- AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */ ++ AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */ ++ AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */ ++ AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read ++ only registers */ ++ AHCI_HFLAG_USE_LPM_POLICY = BIT(25), /* chipset that should use ++ SATA_MOBILE_LPM_POLICY ++ as default lpm_policy */ ++ AHCI_HFLAG_SUSPEND_PHYS = BIT(26), /* handle PHYs during ++ suspend/resume */ ++ AHCI_HFLAG_NO_SXS = BIT(28), /* SXS not supported */ + + /* ap->flags bits */ + +@@ -262,22 +263,22 @@ enum { + EM_MAX_RETRY = 5, + + /* em_ctl bits */ +- EM_CTL_RST = (1 << 9), /* Reset */ +- EM_CTL_TM = (1 << 8), /* Transmit Message */ +- EM_CTL_MR = (1 << 0), /* Message Received */ +- EM_CTL_ALHD = (1 << 26), /* Activity LED */ +- EM_CTL_XMT = (1 << 25), /* Transmit Only */ +- EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ +- EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ +- EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ +- EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ +- EM_CTL_LED = (1 << 16), /* LED messages supported */ ++ EM_CTL_RST = BIT(9), /* Reset */ ++ EM_CTL_TM = BIT(8), /* Transmit Message */ ++ EM_CTL_MR = BIT(0), /* Message Received */ ++ EM_CTL_ALHD = BIT(26), /* Activity LED */ ++ EM_CTL_XMT = BIT(25), /* Transmit Only */ ++ EM_CTL_SMB = BIT(24), /* Single Message Buffer */ ++ EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */ ++ EM_CTL_SES = BIT(18), /* SES-2 messages supported */ ++ EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */ ++ EM_CTL_LED = BIT(16), /* LED messages supported */ + + /* em message type */ +- EM_MSG_TYPE_LED = (1 << 0), /* LED */ +- EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ +- EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ +- EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ ++ EM_MSG_TYPE_LED = BIT(0), /* LED */ ++ EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */ ++ EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */ ++ EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */ + }; + + struct ahci_cmd_hdr { +-- +2.35.1 + diff --git a/queue-6.0/ata-libahci-extend-port-cmd-flags-set-with-port-capa.patch b/queue-6.0/ata-libahci-extend-port-cmd-flags-set-with-port-capa.patch new file mode 100644 index 00000000000..3901361652f --- /dev/null +++ b/queue-6.0/ata-libahci-extend-port-cmd-flags-set-with-port-capa.patch @@ -0,0 +1,70 @@ +From bbaddc5efbc2102fe665eb3e7240bb3533425d21 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 22:36:10 +0300 +Subject: ata: libahci: Extend port-cmd flags set with port capabilities + +From: Serge Semin + +[ Upstream commit eb7cae0b6afda3932d3011285a246b3c6bf26c44 ] + +Currently not all of the Port-specific capabilities listed in the +PORT_CMD-enumeration. Let's extend that set with the Cold Presence +Detection and Mechanical Presence Switch attached to the Port flags [1] so +to closeup the set of the platform-specific port-capabilities flags. Note +these flags are supposed to be set by the platform firmware if there is +one. Alternatively as we are about to do they can be set by means of the +OF properties. + +While at it replace PORT_IRQ_DEV_ILCK with PORT_IRQ_DMPS and fix the +comment there. In accordance with [2] that IRQ flag is supposed to +indicate the state of the signal coming from the Mechanical Presence +Switch. + +[1] Serial ATA AHCI 1.3.1 Specification, p.27 +[2] Serial ATA AHCI 1.3.1 Specification, p.24, p.88 + +Signed-off-by: Serge Semin +Reviewed-by: Hannes Reinecke +Signed-off-by: Damien Le Moal +Stable-dep-of: f07788079f51 ("ata: ahci: fix enum constants for gcc-13") +Signed-off-by: Sasha Levin +--- + drivers/ata/ahci.h | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h +index 6f3286c8506d..60bbea86919c 100644 +--- a/drivers/ata/ahci.h ++++ b/drivers/ata/ahci.h +@@ -139,7 +139,7 @@ enum { + PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ + + PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ +- PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ ++ PORT_IRQ_DMPS = (1 << 7), /* mechanical presence status */ + PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ + PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ + PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ +@@ -167,6 +167,8 @@ enum { + PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ + PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ + PORT_CMD_ESP = (1 << 21), /* External Sata Port */ ++ PORT_CMD_CPD = (1 << 20), /* Cold Presence Detection */ ++ PORT_CMD_MPSP = (1 << 19), /* Mechanical Presence Switch */ + PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ + PORT_CMD_PMP = (1 << 17), /* PMP attached */ + PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ +@@ -182,6 +184,10 @@ enum { + PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ + PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ + ++ /* PORT_CMD capabilities mask */ ++ PORT_CMD_CAP = PORT_CMD_HPCP | PORT_CMD_MPSP | ++ PORT_CMD_CPD | PORT_CMD_ESP | PORT_CMD_FBSCP, ++ + /* PORT_FBS bits */ + PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ + PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ +-- +2.35.1 + diff --git a/queue-6.0/btrfs-fix-uninitialized-parent-in-insert_state.patch b/queue-6.0/btrfs-fix-uninitialized-parent-in-insert_state.patch new file mode 100644 index 00000000000..cc00c01b77e --- /dev/null +++ b/queue-6.0/btrfs-fix-uninitialized-parent-in-insert_state.patch @@ -0,0 +1,44 @@ +From 7737a2b8be5e8a56e4709d938f8d6dfe2b3f3e66 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 18 Nov 2022 15:06:09 -0500 +Subject: btrfs: fix uninitialized parent in insert_state + +From: Josef Bacik + +[ Upstream commit d7c9e1be2876f63fb2178a24e0c1d5733ff98d47 ] + +I don't know how this isn't caught when we build this in the kernel, but +while syncing extent-io-tree.c into btrfs-progs I got an error because +parent could potentially be uninitialized when we link in a new node, +specifically when the extent_io_tree is empty. This means we could have +garbage in the parent color. I don't know what the ramifications are of +that, but it's probably not great, so fix this by initializing parent to +NULL. I spot checked all of our other usages in btrfs and we appear to +be doing the correct thing everywhere else. + +Fixes: c7e118cf98c7 ("btrfs: open code rbtree search in insert_state") +CC: stable@vger.kernel.org # 6.0+ +Signed-off-by: Josef Bacik +Reviewed-by: David Sterba +Signed-off-by: David Sterba +Signed-off-by: Sasha Levin +--- + fs/btrfs/extent_io.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c +index 0982995177a6..f1abd7cf5618 100644 +--- a/fs/btrfs/extent_io.c ++++ b/fs/btrfs/extent_io.c +@@ -558,7 +558,7 @@ static int insert_state(struct extent_io_tree *tree, + u32 bits, struct extent_changeset *changeset) + { + struct rb_node **node; +- struct rb_node *parent; ++ struct rb_node *parent = NULL; + const u64 end = state->end; + + set_state_bits(tree, state, bits, changeset); +-- +2.35.1 + diff --git a/queue-6.0/drm-i915-gt-cleanup-partial-engine-discovery-failure.patch b/queue-6.0/drm-i915-gt-cleanup-partial-engine-discovery-failure.patch new file mode 100644 index 00000000000..a50a95c5b0e --- /dev/null +++ b/queue-6.0/drm-i915-gt-cleanup-partial-engine-discovery-failure.patch @@ -0,0 +1,50 @@ +From 6d8a6bc7de9b15248b1ccd2776da317eac03d7f6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 15 Sep 2022 16:26:51 -0700 +Subject: drm/i915/gt: Cleanup partial engine discovery failures + +From: Chris Wilson + +[ Upstream commit 78a033433a5ae4fee85511ee075bc9a48312c79e ] + +If we abort driver initialisation in the middle of gt/engine discovery, +some engines will be fully setup and some not. Those incompletely setup +engines only have 'engine->release == NULL' and so will leak any of the +common objects allocated. + +v2: + - Drop the destroy_pinned_context() helper for now. It's not really + worth it with just a single callsite at the moment. (Janusz) + +Signed-off-by: Chris Wilson +Cc: Janusz Krzysztofik +Signed-off-by: Matt Roper +Reviewed-by: Janusz Krzysztofik +Link: https://patchwork.freedesktop.org/patch/msgid/20220915232654.3283095-2-matthew.d.roper@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c +index 3dd0af057e6b..ae6464ac3fd9 100644 +--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c +@@ -1333,8 +1333,13 @@ int intel_engines_init(struct intel_gt *gt) + return err; + + err = setup(engine); +- if (err) ++ if (err) { ++ intel_engine_cleanup_common(engine); + return err; ++ } ++ ++ /* The backend should now be responsible for cleanup */ ++ GEM_BUG_ON(engine->release == NULL); + + err = engine_init_common(engine); + if (err) +-- +2.35.1 + diff --git a/queue-6.0/prandom-make-use-of-smaller-types-in-prandom_u32_max.patch b/queue-6.0/prandom-make-use-of-smaller-types-in-prandom_u32_max.patch new file mode 100644 index 00000000000..b585aaf93a7 --- /dev/null +++ b/queue-6.0/prandom-make-use-of-smaller-types-in-prandom_u32_max.patch @@ -0,0 +1,78 @@ +From e754e1774d753d25ab253d2744f9183d37c60c8f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 11:49:35 +0200 +Subject: prandom: make use of smaller types in prandom_u32_max + +From: Jason A. Donenfeld + +[ Upstream commit 4c95236a335d8b62aa8dbd587bed6a5f30d8265a ] + +When possible at compile-time, make use of smaller types in +prandom_u32_max(), so that we can use smaller batches from random.c, +which in turn leads to a 2x or 4x performance boost. This makes a +difference, for example, in kfence, which needs a fast stream of small +numbers (booleans). + +At the same time, we use the occasion to update the old documentation on +these functions. prandom_u32() and prandom_bytes() have direct +replacements now in random.h, while prandom_u32_max() remains useful as +a prandom.h function, since it's not cryptographically secure by virtue +of not being evenly distributed. + +Cc: Dominik Brodowski +Acked-by: Marco Elver +Signed-off-by: Jason A. Donenfeld +Stable-dep-of: e9a688bcb193 ("random: use rejection sampling for uniform bounded random integers") +Signed-off-by: Sasha Levin +--- + include/linux/prandom.h | 17 +++++++++++------ + 1 file changed, 11 insertions(+), 6 deletions(-) + +diff --git a/include/linux/prandom.h b/include/linux/prandom.h +index deace5fb4e62..78db003bc290 100644 +--- a/include/linux/prandom.h ++++ b/include/linux/prandom.h +@@ -12,11 +12,13 @@ + #include + #include + ++/* Deprecated: use get_random_u32 instead. */ + static inline u32 prandom_u32(void) + { + return get_random_u32(); + } + ++/* Deprecated: use get_random_bytes instead. */ + static inline void prandom_bytes(void *buf, size_t nbytes) + { + return get_random_bytes(buf, nbytes); +@@ -37,17 +39,20 @@ void prandom_seed_full_state(struct rnd_state __percpu *pcpu_state); + * prandom_u32_max - returns a pseudo-random number in interval [0, ep_ro) + * @ep_ro: right open interval endpoint + * +- * Returns a pseudo-random number that is in interval [0, ep_ro). Note +- * that the result depends on PRNG being well distributed in [0, ~0U] +- * u32 space. Here we use maximally equidistributed combined Tausworthe +- * generator, that is, prandom_u32(). This is useful when requesting a +- * random index of an array containing ep_ro elements, for example. ++ * Returns a pseudo-random number that is in interval [0, ep_ro). This is ++ * useful when requesting a random index of an array containing ep_ro elements, ++ * for example. The result is somewhat biased when ep_ro is not a power of 2, ++ * so do not use this for cryptographic purposes. + * + * Returns: pseudo-random number in interval [0, ep_ro) + */ + static inline u32 prandom_u32_max(u32 ep_ro) + { +- return (u32)(((u64) prandom_u32() * ep_ro) >> 32); ++ if (__builtin_constant_p(ep_ro <= 1U << 8) && ep_ro <= 1U << 8) ++ return (get_random_u8() * ep_ro) >> 8; ++ if (__builtin_constant_p(ep_ro <= 1U << 16) && ep_ro <= 1U << 16) ++ return (get_random_u16() * ep_ro) >> 16; ++ return ((u64)get_random_u32() * ep_ro) >> 32; + } + + /* +-- +2.35.1 + diff --git a/queue-6.0/random-add-8-bit-and-16-bit-batches.patch b/queue-6.0/random-add-8-bit-and-16-bit-batches.patch new file mode 100644 index 00000000000..09a792c3f27 --- /dev/null +++ b/queue-6.0/random-add-8-bit-and-16-bit-batches.patch @@ -0,0 +1,53 @@ +From eed24c3808a32ebb714950a8240890ec53d2babc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 28 Sep 2022 18:47:30 +0200 +Subject: random: add 8-bit and 16-bit batches + +From: Jason A. Donenfeld + +[ Upstream commit 585cd5fe9f7378601b1d4915ad6e9088333b5e5e ] + +There are numerous places in the kernel that would be sped up by having +smaller batches. Currently those callsites do `get_random_u32() & 0xff` +or similar. Since these are pretty spread out, and will require patches +to multiple different trees, let's get ahead of the curve and lay the +foundation for `get_random_u8()` and `get_random_u16()`, so that it's +then possible to start submitting conversion patches leisurely. + +Signed-off-by: Jason A. Donenfeld +Stable-dep-of: e9a688bcb193 ("random: use rejection sampling for uniform bounded random integers") +Signed-off-by: Sasha Levin +--- + drivers/char/random.c | 2 ++ + include/linux/random.h | 2 ++ + 2 files changed, 4 insertions(+) + +diff --git a/drivers/char/random.c b/drivers/char/random.c +index a04098bc28c1..9dd2cfb8bde9 100644 +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -508,6 +508,8 @@ EXPORT_SYMBOL(get_random_ ##type); + + DEFINE_BATCHED_ENTROPY(u64) + DEFINE_BATCHED_ENTROPY(u32) ++DEFINE_BATCHED_ENTROPY(u16) ++DEFINE_BATCHED_ENTROPY(u8) + + #ifdef CONFIG_SMP + /* +diff --git a/include/linux/random.h b/include/linux/random.h +index 3fec206487f6..f3ba420588cd 100644 +--- a/include/linux/random.h ++++ b/include/linux/random.h +@@ -38,6 +38,8 @@ static inline int unregister_random_vmfork_notifier(struct notifier_block *nb) { + #endif + + void get_random_bytes(void *buf, size_t len); ++u8 get_random_u8(void); ++u16 get_random_u16(void); + u32 get_random_u32(void); + u64 get_random_u64(void); + static inline unsigned int get_random_int(void) +-- +2.35.1 + diff --git a/queue-6.0/random-add-helpers-for-random-numbers-with-given-flo.patch b/queue-6.0/random-add-helpers-for-random-numbers-with-given-flo.patch new file mode 100644 index 00000000000..9b6ec3cba17 --- /dev/null +++ b/queue-6.0/random-add-helpers-for-random-numbers-with-given-flo.patch @@ -0,0 +1,107 @@ +From f6e615641a6845eb4a01e95d07e97a75aa2b0383 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 19 Oct 2022 23:19:35 -0600 +Subject: random: add helpers for random numbers with given floor or range + +From: Jason A. Donenfeld + +[ Upstream commit 7f576b2593a978451416424e75f69ad1e3ae4efe ] + +Now that we have get_random_u32_below(), it's nearly trivial to make +inline helpers to compute get_random_u32_above() and +get_random_u32_inclusive(), which will help clean up open coded loops +and manual computations throughout the tree. + +One snag is that in order to make get_random_u32_inclusive() operate on +closed intervals, we have to do some (unlikely) special case handling if +get_random_u32_inclusive(0, U32_MAX) is called. The least expensive way +of doing this is actually to adjust the slowpath of +get_random_u32_below() to have its undefined 0 result just return the +output of get_random_u32(). We can make this basically free by calling +get_random_u32() before the branch, so that the branch latency gets +interleaved. + +Cc: stable@vger.kernel.org # to ease future backports that use this api +Reviewed-by: Kees Cook +Signed-off-by: Jason A. Donenfeld +Signed-off-by: Sasha Levin +--- + drivers/char/random.c | 18 +++++++++++++++++- + include/linux/random.h | 25 +++++++++++++++++++++++++ + 2 files changed, 42 insertions(+), 1 deletion(-) + +diff --git a/drivers/char/random.c b/drivers/char/random.c +index b5f0d4daf10d..d2abfc0076a4 100644 +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -159,6 +159,8 @@ EXPORT_SYMBOL(wait_for_random_bytes); + * void get_random_bytes(void *buf, size_t len) + * u32 get_random_u32() + * u32 get_random_u32_below(u32 ceil) ++ * u32 get_random_u32_above(u32 floor) ++ * u32 get_random_u32_inclusive(u32 floor, u32 ceil) + * u64 get_random_u64() + * unsigned int get_random_int() + * unsigned long get_random_long() +@@ -523,7 +525,21 @@ u32 __get_random_u32_below(u32 ceil) + * of `-ceil % ceil` is analogous to `2^32 % ceil`, but is computable + * in 32-bits. + */ +- u64 mult = (u64)ceil * get_random_u32(); ++ u32 rand = get_random_u32(); ++ u64 mult; ++ ++ /* ++ * This function is technically undefined for ceil == 0, and in fact ++ * for the non-underscored constant version in the header, we build bug ++ * on that. But for the non-constant case, it's convenient to have that ++ * evaluate to being a straight call to get_random_u32(), so that ++ * get_random_u32_inclusive() can work over its whole range without ++ * undefined behavior. ++ */ ++ if (unlikely(!ceil)) ++ return rand; ++ ++ mult = (u64)ceil * rand; + if (unlikely((u32)mult < ceil)) { + u32 bound = -ceil % ceil; + while (unlikely((u32)mult < bound)) +diff --git a/include/linux/random.h b/include/linux/random.h +index d88af025d97d..feb03df2f2cd 100644 +--- a/include/linux/random.h ++++ b/include/linux/random.h +@@ -95,6 +95,31 @@ static inline u32 get_random_u32_below(u32 ceil) + } + } + ++/* ++ * Returns a random integer in the interval (floor, U32_MAX], with uniform ++ * distribution, suitable for all uses. Fastest when floor is a constant, but ++ * still fast for variable floor as well. ++ */ ++static inline u32 get_random_u32_above(u32 floor) ++{ ++ BUILD_BUG_ON_MSG(__builtin_constant_p(floor) && floor == U32_MAX, ++ "get_random_u32_above() must take floor < U32_MAX"); ++ return floor + 1 + get_random_u32_below(U32_MAX - floor); ++} ++ ++/* ++ * Returns a random integer in the interval [floor, ceil], with uniform ++ * distribution, suitable for all uses. Fastest when floor and ceil are ++ * constant, but still fast for variable floor and ceil as well. ++ */ ++static inline u32 get_random_u32_inclusive(u32 floor, u32 ceil) ++{ ++ BUILD_BUG_ON_MSG(__builtin_constant_p(floor) && __builtin_constant_p(ceil) && ++ (floor > ceil || ceil - floor == U32_MAX), ++ "get_random_u32_inclusive() must take floor <= ceil"); ++ return floor + get_random_u32_below(ceil - floor + 1); ++} ++ + /* + * On 64-bit architectures, protect against non-terminated C string overflows + * by zeroing out the first byte of the canary; this leaves 56 bits of entropy. +-- +2.35.1 + diff --git a/queue-6.0/random-use-rejection-sampling-for-uniform-bounded-ra.patch b/queue-6.0/random-use-rejection-sampling-for-uniform-bounded-ra.patch new file mode 100644 index 00000000000..e69bc621fc0 --- /dev/null +++ b/queue-6.0/random-use-rejection-sampling-for-uniform-bounded-ra.patch @@ -0,0 +1,177 @@ +From b03739091b7db8cdc2fbdfa6c345984631e7a94a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 8 Oct 2022 20:42:54 -0600 +Subject: random: use rejection sampling for uniform bounded random integers + +From: Jason A. Donenfeld + +[ Upstream commit e9a688bcb19348862afe30d7c85bc37c4c293471 ] + +Until the very recent commits, many bounded random integers were +calculated using `get_random_u32() % max_plus_one`, which not only +incurs the price of a division -- indicating performance mostly was not +a real issue -- but also does not result in a uniformly distributed +output if max_plus_one is not a power of two. Recent commits moved to +using `prandom_u32_max(max_plus_one)`, which replaces the division with +a faster multiplication, but still does not solve the issue with +non-uniform output. + +For some users, maybe this isn't a problem, and for others, maybe it is, +but for the majority of users, probably the question has never been +posed and analyzed, and nobody thought much about it, probably assuming +random is random is random. In other words, the unthinking expectation +of most users is likely that the resultant numbers are uniform. + +So we implement here an efficient way of generating uniform bounded +random integers. Through use of compile-time evaluation, and avoiding +divisions as much as possible, this commit introduces no measurable +overhead. At least for hot-path uses tested, any potential difference +was lost in the noise. On both clang and gcc, code generation is pretty +small. + +The new function, get_random_u32_below(), lives in random.h, rather than +prandom.h, and has a "get_random_xxx" function name, because it is +suitable for all uses, including cryptography. + +In order to be efficient, we implement a kernel-specific variant of +Daniel Lemire's algorithm from "Fast Random Integer Generation in an +Interval", linked below. The kernel's variant takes advantage of +constant folding to avoid divisions entirely in the vast majority of +cases, works on both 32-bit and 64-bit architectures, and requests a +minimal amount of bytes from the RNG. + +Link: https://arxiv.org/pdf/1805.10941.pdf +Cc: stable@vger.kernel.org # to ease future backports that use this api +Signed-off-by: Jason A. Donenfeld +Signed-off-by: Sasha Levin +--- + drivers/char/random.c | 22 ++++++++++++++++++++++ + include/linux/prandom.h | 18 ++---------------- + include/linux/random.h | 40 ++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 64 insertions(+), 16 deletions(-) + +diff --git a/drivers/char/random.c b/drivers/char/random.c +index 9dd2cfb8bde9..b5f0d4daf10d 100644 +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -158,6 +158,7 @@ EXPORT_SYMBOL(wait_for_random_bytes); + * + * void get_random_bytes(void *buf, size_t len) + * u32 get_random_u32() ++ * u32 get_random_u32_below(u32 ceil) + * u64 get_random_u64() + * unsigned int get_random_int() + * unsigned long get_random_long() +@@ -511,6 +512,27 @@ DEFINE_BATCHED_ENTROPY(u32) + DEFINE_BATCHED_ENTROPY(u16) + DEFINE_BATCHED_ENTROPY(u8) + ++u32 __get_random_u32_below(u32 ceil) ++{ ++ /* ++ * This is the slow path for variable ceil. It is still fast, most of ++ * the time, by doing traditional reciprocal multiplication and ++ * opportunistically comparing the lower half to ceil itself, before ++ * falling back to computing a larger bound, and then rejecting samples ++ * whose lower half would indicate a range indivisible by ceil. The use ++ * of `-ceil % ceil` is analogous to `2^32 % ceil`, but is computable ++ * in 32-bits. ++ */ ++ u64 mult = (u64)ceil * get_random_u32(); ++ if (unlikely((u32)mult < ceil)) { ++ u32 bound = -ceil % ceil; ++ while (unlikely((u32)mult < bound)) ++ mult = (u64)ceil * get_random_u32(); ++ } ++ return mult >> 32; ++} ++EXPORT_SYMBOL(__get_random_u32_below); ++ + #ifdef CONFIG_SMP + /* + * This function is called when the CPU is coming up, with entry +diff --git a/include/linux/prandom.h b/include/linux/prandom.h +index 78db003bc290..0700dc4768c5 100644 +--- a/include/linux/prandom.h ++++ b/include/linux/prandom.h +@@ -35,24 +35,10 @@ void prandom_seed_full_state(struct rnd_state __percpu *pcpu_state); + #define prandom_init_once(pcpu_state) \ + DO_ONCE(prandom_seed_full_state, (pcpu_state)) + +-/** +- * prandom_u32_max - returns a pseudo-random number in interval [0, ep_ro) +- * @ep_ro: right open interval endpoint +- * +- * Returns a pseudo-random number that is in interval [0, ep_ro). This is +- * useful when requesting a random index of an array containing ep_ro elements, +- * for example. The result is somewhat biased when ep_ro is not a power of 2, +- * so do not use this for cryptographic purposes. +- * +- * Returns: pseudo-random number in interval [0, ep_ro) +- */ ++/* Deprecated: use get_random_u32_below() instead. */ + static inline u32 prandom_u32_max(u32 ep_ro) + { +- if (__builtin_constant_p(ep_ro <= 1U << 8) && ep_ro <= 1U << 8) +- return (get_random_u8() * ep_ro) >> 8; +- if (__builtin_constant_p(ep_ro <= 1U << 16) && ep_ro <= 1U << 16) +- return (get_random_u16() * ep_ro) >> 16; +- return ((u64)get_random_u32() * ep_ro) >> 32; ++ return get_random_u32_below(ep_ro); + } + + /* +diff --git a/include/linux/random.h b/include/linux/random.h +index f3ba420588cd..d88af025d97d 100644 +--- a/include/linux/random.h ++++ b/include/linux/random.h +@@ -55,6 +55,46 @@ static inline unsigned long get_random_long(void) + #endif + } + ++u32 __get_random_u32_below(u32 ceil); ++ ++/* ++ * Returns a random integer in the interval [0, ceil), with uniform ++ * distribution, suitable for all uses. Fastest when ceil is a constant, but ++ * still fast for variable ceil as well. ++ */ ++static inline u32 get_random_u32_below(u32 ceil) ++{ ++ if (!__builtin_constant_p(ceil)) ++ return __get_random_u32_below(ceil); ++ ++ /* ++ * For the fast path, below, all operations on ceil are precomputed by ++ * the compiler, so this incurs no overhead for checking pow2, doing ++ * divisions, or branching based on integer size. The resultant ++ * algorithm does traditional reciprocal multiplication (typically ++ * optimized by the compiler into shifts and adds), rejecting samples ++ * whose lower half would indicate a range indivisible by ceil. ++ */ ++ BUILD_BUG_ON_MSG(!ceil, "get_random_u32_below() must take ceil > 0"); ++ if (ceil <= 1) ++ return 0; ++ for (;;) { ++ if (ceil <= 1U << 8) { ++ u32 mult = ceil * get_random_u8(); ++ if (likely(is_power_of_2(ceil) || (u8)mult >= (1U << 8) % ceil)) ++ return mult >> 8; ++ } else if (ceil <= 1U << 16) { ++ u32 mult = ceil * get_random_u16(); ++ if (likely(is_power_of_2(ceil) || (u16)mult >= (1U << 16) % ceil)) ++ return mult >> 16; ++ } else { ++ u64 mult = (u64)ceil * get_random_u32(); ++ if (likely(is_power_of_2(ceil) || (u32)mult >= -ceil % ceil)) ++ return mult >> 32; ++ } ++ } ++} ++ + /* + * On 64-bit architectures, protect against non-terminated C string overflows + * by zeroing out the first byte of the canary; this leaves 56 bits of entropy. +-- +2.35.1 + diff --git a/queue-6.0/series b/queue-6.0/series new file mode 100644 index 00000000000..bef675fc7aa --- /dev/null +++ b/queue-6.0/series @@ -0,0 +1,9 @@ +drm-i915-gt-cleanup-partial-engine-discovery-failure.patch +random-add-8-bit-and-16-bit-batches.patch +prandom-make-use-of-smaller-types-in-prandom_u32_max.patch +random-use-rejection-sampling-for-uniform-bounded-ra.patch +random-add-helpers-for-random-numbers-with-given-flo.patch +btrfs-fix-uninitialized-parent-in-insert_state.patch +ata-libahci-extend-port-cmd-flags-set-with-port-capa.patch +ata-ahci-fix-enum-constants-for-gcc-13.patch +usb-ulpi-defer-ulpi_register-on-ulpi_read_id-timeout.patch diff --git a/queue-6.0/usb-ulpi-defer-ulpi_register-on-ulpi_read_id-timeout.patch b/queue-6.0/usb-ulpi-defer-ulpi_register-on-ulpi_read_id-timeout.patch new file mode 100644 index 00000000000..76469173fa1 --- /dev/null +++ b/queue-6.0/usb-ulpi-defer-ulpi_register-on-ulpi_read_id-timeout.patch @@ -0,0 +1,49 @@ +From ec5d5cd10770231a116d06bb62e9324ff49076b6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Dec 2022 21:15:26 +0100 +Subject: usb: ulpi: defer ulpi_register on ulpi_read_id timeout + +From: Ferry Toth + +[ Upstream commit 8a7b31d545d3a15f0e6f5984ae16f0ca4fd76aac ] + +Since commit 0f0101719138 ("usb: dwc3: Don't switch OTG -> peripheral +if extcon is present") Dual Role support on Intel Merrifield platform +broke due to rearranging the call to dwc3_get_extcon(). + +It appears to be caused by ulpi_read_id() on the first test write failing +with -ETIMEDOUT. Currently ulpi_read_id() expects to discover the phy via +DT when the test write fails and returns 0 in that case, even if DT does not +provide the phy. As a result usb probe completes without phy. + +Make ulpi_read_id() return -ETIMEDOUT to its user if the first test write +fails. The user should then handle it appropriately. A follow up patch +will make dwc3_core_init() set -EPROBE_DEFER in this case and bail out. + +Fixes: ef6a7bcfb01c ("usb: ulpi: Support device discovery via DT") +Cc: stable@vger.kernel.org +Acked-by: Heikki Krogerus +Signed-off-by: Ferry Toth +Link: https://lore.kernel.org/r/20221205201527.13525-2-ftoth@exalondelft.nl +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/common/ulpi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/common/ulpi.c b/drivers/usb/common/ulpi.c +index 0a4f441aff8f..a834d53a0b66 100644 +--- a/drivers/usb/common/ulpi.c ++++ b/drivers/usb/common/ulpi.c +@@ -207,7 +207,7 @@ static int ulpi_read_id(struct ulpi *ulpi) + /* Test the interface */ + ret = ulpi_write(ulpi, ULPI_SCRATCH, 0xaa); + if (ret < 0) +- goto err; ++ return ret; + + ret = ulpi_read(ulpi, ULPI_SCRATCH); + if (ret < 0) +-- +2.35.1 +