From: Greg Kroah-Hartman Date: Sat, 24 Apr 2021 14:39:56 +0000 (+0200) Subject: 5.11-stable patches X-Git-Tag: v4.4.268~35 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1d00dd2549dc498d0401f757b494c56d1f4173e0;p=thirdparty%2Fkernel%2Fstable-queue.git 5.11-stable patches added patches: drm-amdgpu-fix-gcr_general_cntl-offset-for-dimgrey_cavefish.patch drm-amdgpu-reserve-fence-slot-to-update-page-table.patch --- diff --git a/queue-5.11/drm-amdgpu-fix-gcr_general_cntl-offset-for-dimgrey_cavefish.patch b/queue-5.11/drm-amdgpu-fix-gcr_general_cntl-offset-for-dimgrey_cavefish.patch new file mode 100644 index 00000000000..941fb6dde1b --- /dev/null +++ b/queue-5.11/drm-amdgpu-fix-gcr_general_cntl-offset-for-dimgrey_cavefish.patch @@ -0,0 +1,32 @@ +From 24d034528ef06ad94cfcf4394beac0443ab1b16d Mon Sep 17 00:00:00 2001 +From: Jiansong Chen +Date: Mon, 19 Apr 2021 16:33:22 +0800 +Subject: drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish + +From: Jiansong Chen + +commit 24d034528ef06ad94cfcf4394beac0443ab1b16d upstream. + +dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid, +so follow its registers offset setting. + +Signed-off-by: Jiansong Chen +Reviewed-by: Tao Zhou +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -3280,7 +3280,7 @@ static const struct soc15_reg_golden gol + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), +- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), diff --git a/queue-5.11/drm-amdgpu-reserve-fence-slot-to-update-page-table.patch b/queue-5.11/drm-amdgpu-reserve-fence-slot-to-update-page-table.patch new file mode 100644 index 00000000000..a2f8538751c --- /dev/null +++ b/queue-5.11/drm-amdgpu-reserve-fence-slot-to-update-page-table.patch @@ -0,0 +1,75 @@ +From d42a5b639d15622ece5b9dd12dafd9776efa2593 Mon Sep 17 00:00:00 2001 +From: Philip Yang +Date: Thu, 1 Apr 2021 00:22:23 -0400 +Subject: drm/amdgpu: reserve fence slot to update page table +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Philip Yang + +commit d42a5b639d15622ece5b9dd12dafd9776efa2593 upstream. + +Forgot to reserve a fence slot to use sdma to update page table, cause +below kernel BUG backtrace to handle vm retry fault while application is +exiting. + +[ 133.048143] kernel BUG at /home/yangp/git/compute_staging/kernel/drivers/dma-buf/dma-resv.c:281! +[ 133.048487] Workqueue: events amdgpu_irq_handle_ih1 [amdgpu] +[ 133.048506] RIP: 0010:dma_resv_add_shared_fence+0x204/0x280 +[ 133.048672] amdgpu_vm_sdma_commit+0x134/0x220 [amdgpu] +[ 133.048788] amdgpu_vm_bo_update_range+0x220/0x250 [amdgpu] +[ 133.048905] amdgpu_vm_handle_fault+0x202/0x370 [amdgpu] +[ 133.049031] gmc_v9_0_process_interrupt+0x1ab/0x310 [amdgpu] +[ 133.049165] ? kgd2kfd_interrupt+0x9a/0x180 [amdgpu] +[ 133.049289] ? amdgpu_irq_dispatch+0xb6/0x240 [amdgpu] +[ 133.049408] amdgpu_irq_dispatch+0xb6/0x240 [amdgpu] +[ 133.049534] amdgpu_ih_process+0x9b/0x1c0 [amdgpu] +[ 133.049657] amdgpu_irq_handle_ih1+0x21/0x60 [amdgpu] +[ 133.049669] process_one_work+0x29f/0x640 +[ 133.049678] worker_thread+0x39/0x3f0 +[ 133.049685] ? process_one_work+0x640/0x640 + +Signed-off-by: Philip Yang +Signed-off-by: Felix Kuehling +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 5.11.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -3298,7 +3298,7 @@ bool amdgpu_vm_handle_fault(struct amdgp + struct amdgpu_bo *root; + uint64_t value, flags; + struct amdgpu_vm *vm; +- long r; ++ int r; + + spin_lock(&adev->vm_manager.pasid_lock); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +@@ -3347,6 +3347,12 @@ bool amdgpu_vm_handle_fault(struct amdgp + value = 0; + } + ++ r = dma_resv_reserve_shared(root->tbo.base.resv, 1); ++ if (r) { ++ pr_debug("failed %d to reserve fence slot\n", r); ++ goto error_unlock; ++ } ++ + r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr, + addr, flags, value, NULL, NULL, + NULL); +@@ -3358,7 +3364,7 @@ bool amdgpu_vm_handle_fault(struct amdgp + error_unlock: + amdgpu_bo_unreserve(root); + if (r < 0) +- DRM_ERROR("Can't handle page fault (%ld)\n", r); ++ DRM_ERROR("Can't handle page fault (%d)\n", r); + + error_unref: + amdgpu_bo_unref(&root); diff --git a/queue-5.11/series b/queue-5.11/series index 37d4616fa2d..4c8d85cc8ec 100644 --- a/queue-5.11/series +++ b/queue-5.11/series @@ -2,3 +2,5 @@ vhost-vdpa-protect-concurrent-access-to-vhost-device-iotlb.patch ovl-fix-reference-counting-in-ovl_mmap-error-path.patch coda-fix-reference-counting-in-coda_file_mmap-error-path.patch amd-display-allow-non-linear-multi-planar-formats.patch +drm-amdgpu-reserve-fence-slot-to-update-page-table.patch +drm-amdgpu-fix-gcr_general_cntl-offset-for-dimgrey_cavefish.patch