From: John David Anglin <danglin@gcc.gnu.org>
Date: Thu, 10 Dec 2015 00:46:41 +0000 (+0000)
Subject: re PR target/68729 (../Xbae/Methods.c:1772:1: ICE: in extract_insn, at recog.c:2343)
X-Git-Tag: releases/gcc-4.9.4~457
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1d1fbfe5fab938096b7b80f665898a266ace2554;p=thirdparty%2Fgcc.git

re PR target/68729 (../Xbae/Methods.c:1772:1: ICE: in extract_insn, at recog.c:2343)

	PR target/68729
	* config/pa/pa.c (pa_emit_move_sequence): Don't check that mode is
	consistent with modes of the input and output operands when doing
	reloads to and from floating point registers.  Do reload for all
	address forms.

From-SVN: r231484
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a0e5e2a8b54e..bd387b0019ef 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2015-12-09  John David Anglin  <danglin@gcc.gnu.org>
+
+	PR target/68729
+	* config/pa/pa.c (pa_emit_move_sequence): Don't check that mode is
+	consistent with modes of the input and output operands when doing
+	reloads to and from floating point registers.  Do reload for all
+	address forms.
+
 2015-12-08  Maxim Ostapenko  <m.ostapenko@partner.samsung.com>
 
 	Backport from mainline.
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index c2f03a178bc3..8a703c7e12e9 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1665,11 +1665,10 @@ pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
      REG+D addresses where D does not fit in 5 or 14 bits, including
      (subreg (mem (addr))) cases.  */
   if (scratch_reg
-      && fp_reg_operand (operand0, mode)
+      && FP_REG_P (operand0)
       && (MEM_P (operand1)
 	  || (GET_CODE (operand1) == SUBREG
-	      && MEM_P (XEXP (operand1, 0))))
-      && !floating_point_store_memory_operand (operand1, mode))
+	      && MEM_P (XEXP (operand1, 0)))))
     {
       if (GET_CODE (operand1) == SUBREG)
 	operand1 = XEXP (operand1, 0);
@@ -1681,10 +1680,8 @@ pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
 
       /* D might not fit in 14 bits either; for such cases load D into
 	 scratch reg.  */
-      if (reg_plus_base_memory_operand (operand1, mode)
-	  && !(TARGET_PA_20
-	       && !TARGET_ELF32
-	       && INT_14_BITS (XEXP (XEXP (operand1, 0), 1))))
+      if (reg_plus_base_memory_operand (operand1, GET_MODE (operand1))
+	  && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)))
 	{
 	  emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
 	  emit_move_insn (scratch_reg,
@@ -1700,11 +1697,10 @@ pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
       return 1;
     }
   else if (scratch_reg
-	   && fp_reg_operand (operand1, mode)
+	   && FP_REG_P (operand1)
 	   && (MEM_P (operand0)
 	       || (GET_CODE (operand0) == SUBREG
-		   && MEM_P (XEXP (operand0, 0))))
-	   && !floating_point_store_memory_operand (operand0, mode))
+		   && MEM_P (XEXP (operand0, 0)))))
     {
       if (GET_CODE (operand0) == SUBREG)
 	operand0 = XEXP (operand0, 0);
@@ -1716,10 +1712,8 @@ pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
 
       /* D might not fit in 14 bits either; for such cases load D into
 	 scratch reg.  */
-      if (reg_plus_base_memory_operand (operand0, mode)
-	  && !(TARGET_PA_20
-	       && !TARGET_ELF32
-	       && INT_14_BITS (XEXP (XEXP (operand0, 0), 1))))
+      if (reg_plus_base_memory_operand (operand0, GET_MODE (operand0))
+	  && !INT_14_BITS (XEXP (XEXP (operand0, 0), 1)))
 	{
 	  emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
 	  emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,