From: Maciej W. Rozycki Date: Thu, 20 Nov 2014 11:15:34 +0000 (+0000) Subject: target-mips: Also apply the CP0.Status mask to MTTC0 X-Git-Tag: v2.3.0-rc0~133^2~8 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1d725ae952a14b30c84b7bc81b218b8ba77dd311;p=thirdparty%2Fqemu.git target-mips: Also apply the CP0.Status mask to MTTC0 Make CP0.Status writes made with the MTTC0 instruction respect this register's mask just like all the other places. Also preserve the current values of masked out bits. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1267ef297cf..7e632f6875d 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1413,9 +1413,10 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - other->CP0_Status = arg1 & ~0xf1000018; + other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask); sync_c0_status(env, other, other_tc); }