From: Shenwei Wang Date: Wed, 22 Oct 2025 16:50:25 +0000 (-0400) Subject: arm64: dts: imx8: add default clock rate for usdhc X-Git-Tag: v6.19-rc1~100^2~20^2~86 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1ddf34137c739bec9c7ce0db49c4b5b9eabed62a;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: imx8: add default clock rate for usdhc Add default clock rate for usdhc nodes to support higher transfer speed. Signed-off-by: Shenwei Wang Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index ce6ef160fd550..0b8b32f697681 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -77,6 +77,8 @@ conn_subsys: bus@5b000000 { <&sdhc0_lpcg IMX_LPCG_CLK_5>, <&sdhc0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; status = "disabled"; }; @@ -88,6 +90,8 @@ conn_subsys: bus@5b000000 { <&sdhc1_lpcg IMX_LPCG_CLK_5>, <&sdhc1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; @@ -101,6 +105,8 @@ conn_subsys: bus@5b000000 { <&sdhc2_lpcg IMX_LPCG_CLK_5>, <&sdhc2_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_2>; status = "disabled"; };