From: Your Name <you@example.com>
Date: Sat, 28 Nov 2020 15:37:14 +0000 (+0000)
Subject: MINOR: plock: use an ARMv8 instruction barrier for the pause instruction
X-Git-Tag: v2.4-dev2~9
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1e237d037b3a45ec92d1dfa80dfd2c6bd7fc3af9;p=thirdparty%2Fhaproxy.git

MINOR: plock: use an ARMv8 instruction barrier for the pause instruction

As suggested by @AGSaidi in issue #958, on ARMv8 its convenient to use
an "isb" instruction in pl_cpu_relax() to improve fairness. Without it
I've met a few watchdog conditions on valid locks with 16 threads,
indicating that some threads couldn't manage to get it in 2 seconds. I
never happened again with it. In addition, the performance increased
by slightly more than 5% thanks to the reduced contention.

This should be backported as far as 2.2, possibly even 2.0.
---

diff --git a/include/import/atomic-ops.h b/include/import/atomic-ops.h
index 6fe4c78f4f..1d9c98ba51 100644
--- a/include/import/atomic-ops.h
+++ b/include/import/atomic-ops.h
@@ -524,10 +524,21 @@
 #else
 /* generic implementations */
 
+#if defined(__aarch64__)
+
+/* This was shown to improve fairness on modern ARMv8 such as Neoverse N1 */
+#define pl_cpu_relax() do {				\
+		asm volatile("isb" ::: "memory");	\
+	} while (0)
+
+#else
+
 #define pl_cpu_relax() do {             \
 		asm volatile("");       \
 	} while (0)
 
+#endif
+
 /* full memory barrier */
 #define pl_mb() do {                    \
 		__sync_synchronize();   \