From: Tom Hughes Date: Fri, 4 Nov 2005 18:07:10 +0000 (+0000) Subject: Re-enable a load of tests for instructions which VEX now implements. X-Git-Tag: svn/VALGRIND_3_1_0~224 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1eefeb880d3b822091d9fb1d4d100bec13e95d25;p=thirdparty%2Fvalgrind.git Re-enable a load of tests for instructions which VEX now implements. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5008 --- diff --git a/none/tests/x86/insn_basic.def b/none/tests/x86/insn_basic.def index c09e185962..00906f97c0 100644 --- a/none/tests/x86/insn_basic.def +++ b/none/tests/x86/insn_basic.def @@ -18,8 +18,8 @@ ###aas eflags[0x11,0x10] al.ub[0x9] ah.ub[0x2] : => al.ub[0x3] ah.ub[0x01] eflags[0x11,0x11] ###aas eflags[0x11,0x10] al.ub[0xa] ah.ub[0x2] : => al.ub[0x4] ah.ub[0x01] eflags[0x11,0x11] ###aas eflags[0x11,0x10] al.ub[0xf] ah.ub[0x2] : => al.ub[0x9] ah.ub[0x01] eflags[0x11,0x11] -###adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] -###adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] +adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] +adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] @@ -28,12 +28,12 @@ adcb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46] adcb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47] adcb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46] adcb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47] -###adcb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46] -###adcb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47] +adcb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46] +adcb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47] adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] -###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] -###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] +adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] +adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912] adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913] adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912] @@ -46,8 +46,8 @@ adcw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912] adcw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913] adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334] -###adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999] -###adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000] +adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999] +adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000] adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999] adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000] adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999] @@ -107,66 +107,66 @@ bsrw m16.uw[0x8642] r16.uw[0] => 1.uw[15] bsrl r32.ud[0x13572468] r32.ud[0] => 1.ud[28] bsrl m32.ud[0x75318642] r32.ud[0] => 1.ud[30] bswapl r32.ud[0x12345678] => 0.ud[0x78563412] -###btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] -###btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] -###btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] -###btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] -###btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] -###btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] -###btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] -###btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] -###btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] -###btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] -###btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] -###btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] -###btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] -###btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] -###btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] -###btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] -###btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] -###btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] -###btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] -###btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] +btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] +btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] -###btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] -###btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] -###btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] -###btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] +btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] +btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] -###btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] -###btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] -###btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] -###btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] +btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] +btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] -###btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] -###btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] -###btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] -###btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] +btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] +btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] @@ -175,12 +175,12 @@ cbw al.sb[123] : => ax.sw[123] cbw al.sb[-123] : => ax.sw[-123] cdq eax.ud[0x12345678] : => edx.ud[0x00000000] eax.ud[0x12345678] cdq eax.ud[0xfedcba98] : => edx.ud[0xffffffff] eax.ud[0xfedcba98] -###clc eflags[0x001,0x000] : => eflags[0x001,0x000] -###clc eflags[0x001,0x001] : => eflags[0x001,0x000] +clc eflags[0x001,0x000] : => eflags[0x001,0x000] +clc eflags[0x001,0x001] : => eflags[0x001,0x000] cld eflags[0x400,0x000] : => eflags[0x400,0x000] cld eflags[0x400,0x400] : => eflags[0x400,0x000] -###cmc eflags[0x001,0x000] : => eflags[0x001,0x001] -###cmc eflags[0x001,0x001] : => eflags[0x001,0x000] +cmc eflags[0x001,0x000] : => eflags[0x001,0x001] +cmc eflags[0x001,0x001] : => eflags[0x001,0x000] cmpb imm8[3] al.ub[2] => eflags[0x010,0x010] cmpb imm8[2] al.ub[3] => eflags[0x010,0x000] cmpb imm8[12] al.ub[12] => eflags[0x044,0x044] @@ -466,8 +466,8 @@ incw r16.uw[12345] => 0.uw[12346] incw m16.uw[12345] => 0.uw[12346] incl r32.ud[12345678] => 0.ud[12345679] incl m32.ud[12345678] => 0.ud[12345679] -###lahf eflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7] -###lahf eflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02] +lahf eflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7] +lahf eflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02] movb imm8[123] r8.ub[0] => 1.ub[123] movb imm8[123] m8.ub[0] => 1.ub[123] movb r8.ub[123] r8.ub[0] => 1.ub[123] @@ -533,24 +533,24 @@ orl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779] orl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779] orl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779] orl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779] -###rclb eflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] -###rclb eflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] -###rclb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] -###rclb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] -###rclb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] -###rclb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] -###rclw eflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] -###rclw eflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] -###rclw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] -###rclw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] -###rclw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] -###rclw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] -###rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] -###rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] -###rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] -###rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] -###rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] -###rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +rclb eflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] +rclb eflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] +rclb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +rclb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +rclb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +rclb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] +rclw eflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] +rclw eflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] +rclw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +rclw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +rclw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +rclw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] +rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] +rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] +rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] +rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] rcrb eflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0] rcrb eflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0] rcrb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] @@ -643,8 +643,8 @@ sarl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0] sarl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0] sarl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0] sarl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0] -###sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22] -###sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21] +sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22] +sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21] sbbb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22] sbbb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21] sbbb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22] @@ -653,12 +653,12 @@ sbbb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22] sbbb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21] sbbb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22] sbbb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21] -###sbbb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22] -###sbbb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21] +sbbb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22] +sbbb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21] sbbw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444] sbbw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443] -###sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444] -###sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443] +sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444] +sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443] sbbw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444] sbbw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443] sbbw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444] @@ -671,8 +671,8 @@ sbbw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444] sbbw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443] sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309] sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308] -###sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643] -###sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642] +sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643] +sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642] sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643] sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642] sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643] @@ -943,8 +943,8 @@ shrdl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865] shrdl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865] shrdl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0] shrdl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0] -###stc eflags[0x001,0x000] : => eflags[0x001,0x001] -###stc eflags[0x001,0x001] : => eflags[0x001,0x001] +stc eflags[0x001,0x000] : => eflags[0x001,0x001] +stc eflags[0x001,0x001] : => eflags[0x001,0x001] std eflags[0x400,0x000] : => eflags[0x400,0x400] std eflags[0x400,0x400] : => eflags[0x400,0x400] subb imm8[12] al.ub[34] => 1.ub[22] diff --git a/none/tests/x86/insn_basic.stdout.exp b/none/tests/x86/insn_basic.stdout.exp index 07bba0f36e..db59e409ea 100644 --- a/none/tests/x86/insn_basic.stdout.exp +++ b/none/tests/x86/insn_basic.stdout.exp @@ -6,6 +6,10 @@ adcb_5 ... ok adcb_6 ... ok adcb_7 ... ok adcb_8 ... ok +adcb_9 ... ok +adcb_10 ... ok +adcb_11 ... ok +adcb_12 ... ok adcw_1 ... ok adcw_2 ... ok adcw_3 ... ok @@ -18,6 +22,8 @@ adcw_9 ... ok adcw_10 ... ok adcw_11 ... ok adcw_12 ... ok +adcw_13 ... ok +adcw_14 ... ok adcl_1 ... ok adcl_2 ... ok adcl_3 ... ok @@ -30,6 +36,8 @@ adcl_9 ... ok adcl_10 ... ok adcl_11 ... ok adcl_12 ... ok +adcl_13 ... ok +adcl_14 ... ok addb_1 ... ok addb_2 ... ok addb_3 ... ok @@ -83,40 +91,76 @@ btw_1 ... ok btw_2 ... ok btw_3 ... ok btw_4 ... ok +btw_5 ... ok +btw_6 ... ok +btw_7 ... ok +btw_8 ... ok btl_1 ... ok btl_2 ... ok btl_3 ... ok btl_4 ... ok +btl_5 ... ok +btl_6 ... ok +btl_7 ... ok +btl_8 ... ok btcw_1 ... ok btcw_2 ... ok btcw_3 ... ok btcw_4 ... ok +btcw_5 ... ok +btcw_6 ... ok +btcw_7 ... ok +btcw_8 ... ok btcl_1 ... ok btcl_2 ... ok btcl_3 ... ok btcl_4 ... ok +btcl_5 ... ok +btcl_6 ... ok +btcl_7 ... ok +btcl_8 ... ok btrw_1 ... ok btrw_2 ... ok btrw_3 ... ok btrw_4 ... ok +btrw_5 ... ok +btrw_6 ... ok +btrw_7 ... ok +btrw_8 ... ok btrl_1 ... ok btrl_2 ... ok btrl_3 ... ok btrl_4 ... ok +btrl_5 ... ok +btrl_6 ... ok +btrl_7 ... ok +btrl_8 ... ok btsw_1 ... ok btsw_2 ... ok btsw_3 ... ok btsw_4 ... ok +btsw_5 ... ok +btsw_6 ... ok +btsw_7 ... ok +btsw_8 ... ok btsl_1 ... ok btsl_2 ... ok btsl_3 ... ok btsl_4 ... ok +btsl_5 ... ok +btsl_6 ... ok +btsl_7 ... ok +btsl_8 ... ok cbw_1 ... ok cbw_2 ... ok cdq_1 ... ok cdq_2 ... ok +clc_1 ... ok +clc_2 ... ok cld_1 ... ok cld_2 ... ok +cmc_1 ... ok +cmc_2 ... ok cmpb_1 ... ok cmpb_2 ... ok cmpb_3 ... ok @@ -399,6 +443,8 @@ incw_1 ... ok incw_2 ... ok incl_1 ... ok incl_2 ... ok +lahf_1 ... ok +lahf_2 ... ok movb_1 ... ok movb_2 ... ok movb_3 ... ok @@ -464,6 +510,24 @@ orl_4 ... ok orl_5 ... ok orl_6 ... ok orl_7 ... ok +rclb_1 ... ok +rclb_2 ... ok +rclb_3 ... ok +rclb_4 ... ok +rclb_5 ... ok +rclb_6 ... ok +rclw_1 ... ok +rclw_2 ... ok +rclw_3 ... ok +rclw_4 ... ok +rclw_5 ... ok +rclw_6 ... ok +rcll_1 ... ok +rcll_2 ... ok +rcll_3 ... ok +rcll_4 ... ok +rcll_5 ... ok +rcll_6 ... ok rcrb_1 ... ok rcrb_2 ... ok rcrb_3 ... ok @@ -564,6 +628,10 @@ sbbb_5 ... ok sbbb_6 ... ok sbbb_7 ... ok sbbb_8 ... ok +sbbb_9 ... ok +sbbb_10 ... ok +sbbb_11 ... ok +sbbb_12 ... ok sbbw_1 ... ok sbbw_2 ... ok sbbw_3 ... ok @@ -576,6 +644,8 @@ sbbw_9 ... ok sbbw_10 ... ok sbbw_11 ... ok sbbw_12 ... ok +sbbw_13 ... ok +sbbw_14 ... ok sbbl_1 ... ok sbbl_2 ... ok sbbl_3 ... ok @@ -588,6 +658,8 @@ sbbl_9 ... ok sbbl_10 ... ok sbbl_11 ... ok sbbl_12 ... ok +sbbl_13 ... ok +sbbl_14 ... ok seta_1 ... ok seta_2 ... ok seta_3 ... ok @@ -848,6 +920,8 @@ shrdl_5 ... ok shrdl_6 ... ok shrdl_7 ... ok shrdl_8 ... ok +stc_1 ... ok +stc_2 ... ok std_1 ... ok std_2 ... ok subb_1 ... ok