From: Andrey Belevantsev Date: Thu, 4 Apr 2013 14:04:21 +0000 (+0400) Subject: backport: re PR rtl-optimization/54472 (ICE (spill_failure): unable to find a registe... X-Git-Tag: releases/gcc-4.6.4~57 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1f59be86ba76b6e38d3b71d01675a891e4f46f05;p=thirdparty%2Fgcc.git backport: re PR rtl-optimization/54472 (ICE (spill_failure): unable to find a register to spill in class 'AREG' with -O -fschedule-insns -fselective-scheduling) 2013-04-04 Andrey Belevantsev Backport from mainline 2012-11-09 Andrey Belevantsev PR rtl-optimization/54472 * sel-sched-ir.c (has_dependence_note_reg_set): Handle implicit sets. (has_dependence_note_reg_clobber, as_dependence_note_reg_use): Likewise. 2012-11-09 Andrey Belevantsev PR rtl-optimization/54472 * gcc.dg/pr54472.c: New test. From-SVN: r197483 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f9b7ec9c8b58..57e0196e97f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2013-04-04 Andrey Belevantsev + + Backport from mainline + 2012-11-09 Andrey Belevantsev + + PR rtl-optimization/54472 + * sel-sched-ir.c (has_dependence_note_reg_set): Handle implicit sets. + (has_dependence_note_reg_clobber, + as_dependence_note_reg_use): Likewise. + 2013-04-04 Marek Polacek Backported from mainline diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c index 38c817eca370..38aaff67bd60 100644 --- a/gcc/sel-sched-ir.c +++ b/gcc/sel-sched-ir.c @@ -3110,7 +3110,7 @@ has_dependence_note_reg_set (int regno) || reg_last->clobbers != NULL) *dsp = (*dsp & ~SPECULATIVE) | DEP_OUTPUT; - if (reg_last->uses) + if (reg_last->uses || reg_last->implicit_sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI; } } @@ -3130,7 +3130,7 @@ has_dependence_note_reg_clobber (int regno) if (reg_last->sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_OUTPUT; - if (reg_last->uses) + if (reg_last->uses || reg_last->implicit_sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI; } } @@ -3150,7 +3150,7 @@ has_dependence_note_reg_use (int regno) if (reg_last->sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_TRUE; - if (reg_last->clobbers) + if (reg_last->clobbers || reg_last->implicit_sets) *dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI; /* Handle BE_IN_SPEC. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 80016c5622ff..bc83fcf4e98c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2013-04-04 Andrey Belevantsev + + Backport from mainline + 2012-11-09 Andrey Belevantsev + + PR rtl-optimization/54472 + * gcc.dg/pr54472.c: New test. + 2013-04-04 Marek Polacek Backported from mainline diff --git a/gcc/testsuite/gcc.dg/pr54472.c b/gcc/testsuite/gcc.dg/pr54472.c new file mode 100644 index 000000000000..93952038ec41 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr54472.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns -fselective-scheduling" } */ + +int main () +{ + int a[3][3][3]; + __builtin_memset (a, 0, sizeof a); + return 0; +}