From: krebbel Date: Mon, 19 Mar 2007 08:51:20 +0000 (+0000) Subject: 2007-03-19 Andreas Krebbel X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1f8e70bcbe8f8eb0c71dfe66cc349170357ab6bb;p=thirdparty%2Fgcc.git 2007-03-19 Andreas Krebbel * config/s390/s390.md (op_type attribute): RRR instruction type added. (FP, DFP, SD_SF, DD_DF, TD_TF): New mode macros. (xde, xdee): Mode attributes adjusted to support DFP modes. (RRer, f0, op1, Rf, bt, bfp, HALF_TMODE): New mode attributes added. ("cmp", "*cmp_css_0", "*cmp_ccs", TF move splitters, DF move splitters, "floatdi2", "add3", "*add3", "*add3_cc", "*add3_cconly", "sub3", "*sub3", "*sub3_cc", "*sub3_cconly", "mul3", "*mul3", "div3", "*div3", "*neg2_nocc", "*abs2_nocc", "*negabs2_nocc", "copysign3"): Adjusted to support DFP numbers. ("*movtf_64", "*movtf_31", "*movdf_64dfp", "*movdf_64", "*movdf_31", "movsf"): Insn definitions removed. ("*mov_64", "*mov_31", "mov", "*mov_64dfp", "*mov_64", "*mov_31", "fix_truncdi2", "trunctddd2", "truncddsd2", "extendddtd2", "extendsddd2"): Insn definitions added. ("fixuns_truncdddi2", "fixuns_trunctddi2", "mov", "reload_in", "reload_out"): Expander added. ("movtf", "movdf", "reload_outtf", "reload_outdf", "reload_intf"): Expander removed. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@123058 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d4f136e039b4..2e8292db8173 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,27 @@ +2007-03-19 Andreas Krebbel + + * config/s390/s390.md (op_type attribute): RRR instruction type added. + (FP, DFP, SD_SF, DD_DF, TD_TF): New mode macros. + (xde, xdee): Mode attributes adjusted to support DFP modes. + (RRer, f0, op1, Rf, bt, bfp, HALF_TMODE): New mode attributes added. + ("cmp", "*cmp_css_0", "*cmp_ccs", TF move splitters, + DF move splitters, "floatdi2", "add3", "*add3", + "*add3_cc", "*add3_cconly", "sub3", "*sub3", + "*sub3_cc", "*sub3_cconly", "mul3", "*mul3", + "div3", "*div3", "*neg2_nocc", "*abs2_nocc", + "*negabs2_nocc", "copysign3"): Adjusted to support DFP + numbers. + ("*movtf_64", "*movtf_31", "*movdf_64dfp", "*movdf_64", "*movdf_31", + "movsf"): Insn definitions removed. + ("*mov_64", "*mov_31", "mov", "*mov_64dfp", + "*mov_64", "*mov_31", "fix_truncdi2", + "trunctddd2", "truncddsd2", "extendddtd2", "extendsddd2"): Insn + definitions added. + ("fixuns_truncdddi2", "fixuns_trunctddi2", "mov", + "reload_in", "reload_out"): Expander added. + ("movtf", "movdf", "reload_outtf", "reload_outdf", "reload_intf"): + Expander removed. + 2007-03-19 Andreas Krebbel * config/s390/s390.md: Only non-functional changes. Renamed diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 27733a02fbbb..19e8402b5db3 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -152,7 +152,7 @@ ;; Used to determine defaults for length and other attribute values. (define_attr "op_type" - "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF" + "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR" (const_string "NN")) ;; Instruction type attribute used for scheduling. @@ -214,8 +214,13 @@ ;; This mode macro allows floating point patterns to be generated from the ;; same template. +(define_mode_macro FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) (define_mode_macro BFP [TF DF SF]) +(define_mode_macro DFP [TD DD]) (define_mode_macro DSF [DF SF]) +(define_mode_macro SD_SF [SF SD]) +(define_mode_macro DD_DF [DF DD]) +(define_mode_macro TD_TF [TF TD]) ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated ;; from the same template. @@ -255,23 +260,37 @@ (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") (plus "add") (minus "sub") (mult "nand")]) +;; In FP templates, a string like "ltbr" will expand to "ltxbr" in +;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. +(define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) -;; In BFP templates, a string like "ltbr" will expand to "ltxbr" in TFmode, -;; "ltdbr" in DFmode, and "ltebr" in SFmode. -(define_mode_attr xde [(TF "x") (DF "d") (SF "e")]) +;; In FP templates, a in "mr" will expand to "mxr" in +;; TF/TDmode, "mdr" in DF/DDmode, "meer" in SFmode and "mer in +;; SDmode. +(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) -;; In BFP templates, a string like "mbr" will expand to "mxbr" in TFmode, -;; "mdbr" in DFmode, and "meebr" in SFmode. -(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")]) - -;; In BFP templates, "" will expand to "RRE" in TFmode and "RR" otherwise. +;; In FP templates, "" will expand to "RRE" in TFmode and "RR" otherwise. ;; Likewise for "". (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) -;; In BFP templates, "" will expand to "f" in TFmode and "R" otherwise. -;; This is used to disable the memory alternative in TFmode patterns. -(define_mode_attr Rf [(TF "f") (DF "R") (SF "R")]) +;; The decimal floating point variants of add, sub, div and mul support 3 +;; fp register operands. The following macros allow to merge the bfp and +;; dfp variants in a single insn definition. + +;; This macro is used to set op_type accordingly. +(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") + (DD "RRR") (SD "RRR")]) + +;; This macro is used in the operand constraint list in order to have the +;; first and the second operand match for bfp modes. +(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) + +;; This macro is used in the operand list of the instruction to have an +;; additional operand for the dfp instructions. +(define_mode_attr op1 [(TF "") (DF "") (SF "") + (TD "%1,") (DD "%1,") (SD "%1,")]) + ;; This attribute is used in the operand constraint list ;; for instructions dealing with the sign bit of 32 or 64bit fp values. @@ -281,6 +300,20 @@ ;; target operand uses the same fp register. (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) +;; In FP templates, "" will expand to "f" in TFmode and "R" otherwise. +;; This is used to disable the memory alternative in TFmode patterns. +(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) + +;; This macro adds b for bfp instructions and t for dfp instructions and is used +;; within instruction mnemonics. +(define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) + +;; Although it is unprecise for z9-ec we handle all dfp instructions like +;; bfp regarding the pipeline description. +(define_mode_attr bfp [(TF "tf") (DF "df") (SF "sf") + (TD "tf") (DD "df") (SD "sf")]) + + ;; In GPR and P templates, a constraint like "" will expand to "d" in DImode ;; and "0" in SImode. This allows to combine instructions of which the 31bit ;; version only operates on one register. @@ -341,6 +374,10 @@ ;; in SImode. (define_mode_attr DBL [(DI "TI") (SI "DI")]) +;; This attribute expands to DF for TFmode and to DD for TDmode . It is +;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. +(define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) + ;; Maximum unsigned integer that fits in MODE. (define_mode_attr max_uint [(HI "65535") (QI "255")]) @@ -362,8 +399,8 @@ (define_expand "cmp" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:BFP 0 "register_operand" "") - (match_operand:BFP 1 "general_operand" "")))] + (compare:CC (match_operand:FP 0 "register_operand" "") + (match_operand:FP 1 "general_operand" "")))] "TARGET_HARD_FLOAT" { s390_compare_op0 = operands[0]; @@ -748,17 +785,17 @@ }) -; (DF|SF) instructions +; (TF|DF|SF|TD|DD|SD) instructions -; ltxbr, ltdbr, ltebr +; ltxbr, ltdbr, ltebr, ltxtr, ltdtr (define_insn "*cmp_ccs_0" [(set (reg CC_REGNUM) - (compare (match_operand:BFP 0 "register_operand" "f") - (match_operand:BFP 1 "const0_operand" "")))] + (compare (match_operand:FP 0 "register_operand" "f") + (match_operand:FP 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "ltbr\t%0,%0" + "ltr\t%0,%0" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimp")]) + (set_attr "type" "fsimp")]) ; ltxr, ltdr, lter (define_insn "*cmp_ccs_0_ibm" @@ -770,17 +807,17 @@ [(set_attr "op_type" "") (set_attr "type" "fsimp")]) -; cxbr, cdbr, cebr, cxb, cdb, ceb +; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr (define_insn "*cmp_ccs" [(set (reg CC_REGNUM) - (compare (match_operand:BFP 0 "register_operand" "f,f") - (match_operand:BFP 1 "general_operand" "f,")))] + (compare (match_operand:FP 0 "register_operand" "f,f") + (match_operand:FP 1 "general_operand" "f,")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - cbr\t%0,%1 + cr\t%0,%1 cb\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp")]) + (set_attr "type" "fsimp")]) ; cxr, cdr, cer, cx, cd, ce (define_insn "*cmp_ccs_ibm" @@ -1472,18 +1509,18 @@ (set_attr "type" "lr,load,load,*")]) ; -; movtf instruction pattern(s). +; mov(tf|td) instruction pattern(s). ; -(define_expand "movtf" - [(set (match_operand:TF 0 "nonimmediate_operand" "") - (match_operand:TF 1 "general_operand" ""))] +(define_expand "mov" + [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") + (match_operand:TD_TF 1 "general_operand" ""))] "" "") -(define_insn "*movtf_64" - [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,d,QS,d,o,Q") - (match_operand:TF 1 "general_operand" "G,f,o,f,QS,d,dm,d,Q"))] +(define_insn "*mov_64" + [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o,Q") + (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dm,d,Q"))] "TARGET_64BIT" "@ lzxr\t%0 @@ -1498,9 +1535,9 @@ [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*") (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")]) -(define_insn "*movtf_31" - [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,Q") - (match_operand:TF 1 "general_operand" "G,f,o,f,Q"))] +(define_insn "*mov_31" + [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,Q") + (match_operand:TD_TF 1 "general_operand" " G,f,o,f,Q"))] "!TARGET_64BIT" "@ lzxr\t%0 @@ -1514,42 +1551,42 @@ ; TFmode in GPRs splitters (define_split - [(set (match_operand:TF 0 "nonimmediate_operand" "") - (match_operand:TF 1 "general_operand" ""))] + [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") + (match_operand:TD_TF 1 "general_operand" ""))] "TARGET_64BIT && reload_completed - && s390_split_ok_p (operands[0], operands[1], TFmode, 0)" + && s390_split_ok_p (operands[0], operands[1], mode, 0)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] { - operands[2] = operand_subword (operands[0], 0, 0, TFmode); - operands[3] = operand_subword (operands[0], 1, 0, TFmode); - operands[4] = operand_subword (operands[1], 0, 0, TFmode); - operands[5] = operand_subword (operands[1], 1, 0, TFmode); + operands[2] = operand_subword (operands[0], 0, 0, mode); + operands[3] = operand_subword (operands[0], 1, 0, mode); + operands[4] = operand_subword (operands[1], 0, 0, mode); + operands[5] = operand_subword (operands[1], 1, 0, mode); }) (define_split - [(set (match_operand:TF 0 "nonimmediate_operand" "") - (match_operand:TF 1 "general_operand" ""))] + [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") + (match_operand:TD_TF 1 "general_operand" ""))] "TARGET_64BIT && reload_completed - && s390_split_ok_p (operands[0], operands[1], TFmode, 1)" + && s390_split_ok_p (operands[0], operands[1], mode, 1)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] { - operands[2] = operand_subword (operands[0], 1, 0, TFmode); - operands[3] = operand_subword (operands[0], 0, 0, TFmode); - operands[4] = operand_subword (operands[1], 1, 0, TFmode); - operands[5] = operand_subword (operands[1], 0, 0, TFmode); + operands[2] = operand_subword (operands[0], 1, 0, mode); + operands[3] = operand_subword (operands[0], 0, 0, mode); + operands[4] = operand_subword (operands[1], 1, 0, mode); + operands[5] = operand_subword (operands[1], 0, 0, mode); }) (define_split - [(set (match_operand:TF 0 "register_operand" "") - (match_operand:TF 1 "memory_operand" ""))] + [(set (match_operand:TD_TF 0 "register_operand" "") + (match_operand:TD_TF 1 "memory_operand" ""))] "TARGET_64BIT && reload_completed && !FP_REG_P (operands[0]) && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] { - rtx addr = operand_subword (operands[0], 1, 0, DFmode); + rtx addr = operand_subword (operands[0], 1, 0, mode); s390_load_address (addr, XEXP (operands[1], 0)); operands[1] = replace_equiv_address (operands[1], addr); }) @@ -1557,37 +1594,41 @@ ; TFmode in BFPs splitters (define_split - [(set (match_operand:TF 0 "register_operand" "") - (match_operand:TF 1 "memory_operand" ""))] + [(set (match_operand:TD_TF 0 "register_operand" "") + (match_operand:TD_TF 1 "memory_operand" ""))] "reload_completed && offsettable_memref_p (operands[1]) && FP_REG_P (operands[0])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] { - operands[2] = simplify_gen_subreg (DFmode, operands[0], TFmode, 0); - operands[3] = simplify_gen_subreg (DFmode, operands[0], TFmode, 8); - operands[4] = adjust_address_nv (operands[1], DFmode, 0); - operands[5] = adjust_address_nv (operands[1], DFmode, 8); + operands[2] = simplify_gen_subreg (mode, operands[0], + mode, 0); + operands[3] = simplify_gen_subreg (mode, operands[0], + mode, 8); + operands[4] = adjust_address_nv (operands[1], mode, 0); + operands[5] = adjust_address_nv (operands[1], mode, 8); }) (define_split - [(set (match_operand:TF 0 "memory_operand" "") - (match_operand:TF 1 "register_operand" ""))] + [(set (match_operand:TD_TF 0 "memory_operand" "") + (match_operand:TD_TF 1 "register_operand" ""))] "reload_completed && offsettable_memref_p (operands[0]) && FP_REG_P (operands[1])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] { - operands[2] = adjust_address_nv (operands[0], DFmode, 0); - operands[3] = adjust_address_nv (operands[0], DFmode, 8); - operands[4] = simplify_gen_subreg (DFmode, operands[1], TFmode, 0); - operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, 8); + operands[2] = adjust_address_nv (operands[0], mode, 0); + operands[3] = adjust_address_nv (operands[0], mode, 8); + operands[4] = simplify_gen_subreg (mode, operands[1], + mode, 0); + operands[5] = simplify_gen_subreg (mode, operands[1], + mode, 8); }) -(define_expand "reload_outtf" - [(parallel [(match_operand:TF 0 "" "") - (match_operand:TF 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "=&a")])] +(define_expand "reload_out" + [(parallel [(match_operand:TD_TF 0 "" "") + (match_operand:TD_TF 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "=&a")])] "" { rtx addr = gen_lowpart (Pmode, operands[2]); @@ -1599,10 +1640,10 @@ DONE; }) -(define_expand "reload_intf" - [(parallel [(match_operand:TF 0 "register_operand" "=f") - (match_operand:TF 1 "" "") - (match_operand:SI 2 "register_operand" "=&a")])] +(define_expand "reload_in" + [(parallel [(match_operand:TD_TF 0 "register_operand" "=f") + (match_operand:TD_TF 1 "" "") + (match_operand:SI 2 "register_operand" "=&a")])] "" { rtx addr = gen_lowpart (Pmode, operands[2]); @@ -1615,20 +1656,20 @@ }) ; -; movdf instruction pattern(s). +; mov(df|dd) instruction pattern(s). ; -(define_expand "movdf" - [(set (match_operand:DF 0 "nonimmediate_operand" "") - (match_operand:DF 1 "general_operand" ""))] +(define_expand "mov" + [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") + (match_operand:DD_DF 1 "general_operand" ""))] "" "") -(define_insn "*movdf_64dfp" - [(set (match_operand:DF 0 "nonimmediate_operand" - "=f,f,f,d,f,f,R,T,d,d,m,?Q") - (match_operand:DF 1 "general_operand" - "G,f,d,f,R,T,f,f,d,m,d,?Q"))] +(define_insn "*mov_64dfp" + [(set (match_operand:DD_DF 0 "nonimmediate_operand" + "=f,f,f,d,f,f,R,T,d,d,m,?Q") + (match_operand:DD_DF 1 "general_operand" + "G,f,d,f,R,T,f,f,d,m,d,?Q"))] "TARGET_64BIT && TARGET_DFP" "@ lzdr\t%0 @@ -1647,9 +1688,9 @@ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, fstoredf,fstoredf,lr,load,store,*")]) -(define_insn "*movdf_64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q") - (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))] +(define_insn "*mov_64" + [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q") + (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))] "TARGET_64BIT" "@ lzdr\t%0 @@ -1663,11 +1704,14 @@ stg\t%1,%0 #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") - (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")]) - -(define_insn "*movdf_31" - [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q") - (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))] + (set_attr "type" "fsimp,fload,fload,fload, + fstore,fstore,lr,load,store,*")]) + +(define_insn "*mov_31" + [(set (match_operand:DD_DF 0 "nonimmediate_operand" + "=f,f,f,f,R,T,d,d,Q,S, d,o,Q") + (match_operand:DD_DF 1 "general_operand" + " G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))] "!TARGET_64BIT" "@ lzdr\t%0 @@ -1684,54 +1728,54 @@ # #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS") - (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\ - lm,lm,stm,stm,*,*,*")]) + (set_attr "type" "fsimp,fload,fload,fload, + fstore,fstore,lm,lm,stm,stm,*,*,*")]) (define_split - [(set (match_operand:DF 0 "nonimmediate_operand" "") - (match_operand:DF 1 "general_operand" ""))] + [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") + (match_operand:DD_DF 1 "general_operand" ""))] "!TARGET_64BIT && reload_completed - && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" + && s390_split_ok_p (operands[0], operands[1], mode, 0)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] { - operands[2] = operand_subword (operands[0], 0, 0, DFmode); - operands[3] = operand_subword (operands[0], 1, 0, DFmode); - operands[4] = operand_subword (operands[1], 0, 0, DFmode); - operands[5] = operand_subword (operands[1], 1, 0, DFmode); + operands[2] = operand_subword (operands[0], 0, 0, mode); + operands[3] = operand_subword (operands[0], 1, 0, mode); + operands[4] = operand_subword (operands[1], 0, 0, mode); + operands[5] = operand_subword (operands[1], 1, 0, mode); }) (define_split - [(set (match_operand:DF 0 "nonimmediate_operand" "") - (match_operand:DF 1 "general_operand" ""))] + [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") + (match_operand:DD_DF 1 "general_operand" ""))] "!TARGET_64BIT && reload_completed - && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" + && s390_split_ok_p (operands[0], operands[1], mode, 1)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] { - operands[2] = operand_subword (operands[0], 1, 0, DFmode); - operands[3] = operand_subword (operands[0], 0, 0, DFmode); - operands[4] = operand_subword (operands[1], 1, 0, DFmode); - operands[5] = operand_subword (operands[1], 0, 0, DFmode); + operands[2] = operand_subword (operands[0], 1, 0, mode); + operands[3] = operand_subword (operands[0], 0, 0, mode); + operands[4] = operand_subword (operands[1], 1, 0, mode); + operands[5] = operand_subword (operands[1], 0, 0, mode); }) (define_split - [(set (match_operand:DF 0 "register_operand" "") - (match_operand:DF 1 "memory_operand" ""))] + [(set (match_operand:DD_DF 0 "register_operand" "") + (match_operand:DD_DF 1 "memory_operand" ""))] "!TARGET_64BIT && reload_completed && !FP_REG_P (operands[0]) && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] { - rtx addr = operand_subword (operands[0], 1, 0, DFmode); + rtx addr = operand_subword (operands[0], 1, 0, mode); s390_load_address (addr, XEXP (operands[1], 0)); operands[1] = replace_equiv_address (operands[1], addr); }) -(define_expand "reload_outdf" - [(parallel [(match_operand:DF 0 "" "") - (match_operand:DF 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "=&a")])] +(define_expand "reload_out" + [(parallel [(match_operand:DD_DF 0 "" "") + (match_operand:DD_DF 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "=&a")])] "!TARGET_64BIT" { gcc_assert (MEM_P (operands[0])); @@ -1742,12 +1786,14 @@ }) ; -; movsf instruction pattern(s). +; mov(sf|sd) instruction pattern(s). ; -(define_insn "movsf" - [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q") - (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))] +(define_insn "mov" + [(set (match_operand:SD_SF 0 "nonimmediate_operand" + "=f,f,f,f,R,T,d,d,d,R,T,?Q") + (match_operand:SD_SF 1 "general_operand" + " G,f,R,T,f,f,d,R,T,d,d,?Q"))] "" "@ lzer\t%0 @@ -1763,8 +1809,8 @@ sty\t%1,%0 #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") - (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf, - lr,load,load,store,store,*")]) + (set_attr "type" "fsimp,fload,fload,fload, + fstore,fstore,lr,load,load,store,store,*")]) ; ; movcc instruction pattern @@ -3143,9 +3189,76 @@ (set (strict_low_part (match_dup 2)) (match_dup 1))] "operands[2] = gen_lowpart (QImode, operands[0]);") +; +; fixuns_trunc(dd|td)di2 instruction pattern(s). +; + +(define_expand "fixuns_truncdddi2" + [(parallel + [(set (match_operand:DI 0 "register_operand" "") + (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) + (clobber (match_scratch:TD 2 "=f"))])] + + "TARGET_HARD_FLOAT && TARGET_HARD_DFP" +{ + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + rtx temp = gen_reg_rtx (TDmode); + REAL_VALUE_TYPE cmp, sub; + + decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ + decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ + + /* 2^63 can't be represented as 64bit DFP number with full precision. The + solution is doing the check and the subtraction in TD mode and using a + TD -> DI convert afterwards. */ + emit_insn (gen_extendddtd2 (temp, operands[1])); + temp = force_reg (TDmode, temp); + emit_insn (gen_cmptd (temp, + CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); + emit_jump_insn (gen_blt (label1)); + emit_insn (gen_subtd3 (temp, temp, + CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); + emit_insn (gen_fix_trunctddi2 (operands[0], temp, GEN_INT(11))); + emit_jump (label2); + + emit_label (label1); + emit_insn (gen_fix_truncdddi2 (operands[0], operands[1], GEN_INT(9))); + emit_label (label2); + DONE; +}) + +(define_expand "fixuns_trunctddi2" + [(set (match_operand:DI 0 "register_operand" "") + (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))] + "TARGET_HARD_FLOAT && TARGET_HARD_DFP" +{ + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + rtx temp = gen_reg_rtx (TDmode); + REAL_VALUE_TYPE cmp, sub; + + operands[1] = force_reg (TDmode, operands[1]); + decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ + decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ + + emit_insn (gen_cmptd (operands[1], + CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); + emit_jump_insn (gen_blt (label1)); + emit_insn (gen_subtd3 (temp, operands[1], + CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); + emit_insn (gen_fix_trunctddi2 (operands[0], temp, GEN_INT(11))); + emit_jump (label2); + + emit_label (label1); + emit_insn (gen_fix_trunctddi2 (operands[0], operands[1], GEN_INT(9))); + emit_label (label2); + DONE; +}) ; -; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s). +; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 +; instruction pattern(s). ; (define_expand "fixuns_trunc2" @@ -3200,6 +3313,23 @@ [(set_attr "op_type" "RRE") (set_attr "type" "ftoi")]) + +; +; fix_trunc(td|dd)di2 instruction pattern(s). +; + +; cgxtr, cgdtr +(define_insn "fix_truncdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (fix:DI (match_operand:DFP 1 "register_operand" "f"))) + (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) + (clobber (reg:CC CC_REGNUM))] + "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP" + "cgtr\t%0,%h2,%1" + [(set_attr "op_type" "RRF") + (set_attr "type" "ftoi")]) + + ; ; fix_trunctf(si|di)2 instruction pattern(s). ; @@ -3288,12 +3418,12 @@ ; float(si|di)(tf|df|sf)2 instruction pattern(s). ; -; cxgbr, cdgbr, cegbr +; cxgbr, cdgbr, cegbr, cxgtr, cdgtr (define_insn "floatdi2" - [(set (match_operand:BFP 0 "register_operand" "=f") - (float:BFP (match_operand:DI 1 "register_operand" "d")))] + [(set (match_operand:FP 0 "register_operand" "=f") + (float:FP (match_operand:DI 1 "register_operand" "d")))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cgbr\t%0,%1" + "cgr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "itof" )]) @@ -3457,6 +3587,26 @@ [(set_attr "length" "6") (set_attr "type" "ftrunctf")]) +; +; trunctddd2 and truncddsd2 instruction pattern(s). +; + +(define_insn "trunctddd2" + [(set (match_operand:DD 0 "register_operand" "=f") + (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_HARD_DFP" + "ldxtr\t%0,0,%1,0" + [(set_attr "op_type" "RRF") + (set_attr "type" "fsimptf")]) + +(define_insn "truncddsd2" + [(set (match_operand:SD 0 "register_operand" "=f") + (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_HARD_DFP" + "ledtr\t%0,0,%1,0" + [(set_attr "op_type" "RRF") + (set_attr "type" "fsimptf")]) + ; ; extendsfdf2 instruction pattern(s). ; @@ -3554,6 +3704,25 @@ [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimptf, floadtf")]) +; +; extendddtd2 and extendsddd2 instruction pattern(s). +; + +(define_insn "extendddtd2" + [(set (match_operand:TD 0 "register_operand" "=f") + (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_HARD_DFP" + "lxdtr\t%0,%1,0" + [(set_attr "op_type" "RRF") + (set_attr "type" "fsimptf")]) + +(define_insn "extendsddd2" + [(set (match_operand:DD 0 "register_operand" "=f") + (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_HARD_DFP" + "ldetr\t%0,%1,0" + [(set_attr "op_type" "RRF") + (set_attr "type" "fsimptf")]) ;; ;; ARITHMETIC OPERATIONS @@ -3878,59 +4047,59 @@ [(set_attr "op_type" "RI,RIL")]) ; -; add(df|sf)3 instruction pattern(s). +; add(tf|df|sf|td|dd)3 instruction pattern(s). ; (define_expand "add3" [(parallel - [(set (match_operand:BFP 0 "register_operand" "=f,f") - (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0") - (match_operand:BFP 2 "general_operand" "f,"))) + [(set (match_operand:FP 0 "register_operand" "") + (plus:FP (match_operand:FP 1 "nonimmediate_operand" "") + (match_operand:FP 2 "general_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") -; axbr, adbr, aebr, axb, adb, aeb +; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add3" - [(set (match_operand:BFP 0 "register_operand" "=f,f") - (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0") - (match_operand:BFP 2 "general_operand" "f,"))) + [(set (match_operand:FP 0 "register_operand" "=f, f") + (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%,0") + (match_operand:FP 2 "general_operand" " f,"))) (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - abr\t%0,%2 + ar\t%0,%2 ab\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" ",RXE") + (set_attr "type" "fsimp")]) -; axbr, adbr, aebr, axb, adb, aeb +; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add3_cc" [(set (reg CC_REGNUM) - (compare (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0") - (match_operand:BFP 2 "general_operand" "f,")) - (match_operand:BFP 3 "const0_operand" ""))) - (set (match_operand:BFP 0 "register_operand" "=f,f") - (plus:BFP (match_dup 1) (match_dup 2)))] + (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%,0") + (match_operand:FP 2 "general_operand" " f,")) + (match_operand:FP 3 "const0_operand" ""))) + (set (match_operand:FP 0 "register_operand" "=f,f") + (plus:FP (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - abr\t%0,%2 + ar\t%0,%2 ab\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" ",RXE") + (set_attr "type" "fsimp")]) -; axbr, adbr, aebr, axb, adb, aeb +; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add3_cconly" [(set (reg CC_REGNUM) - (compare (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0") - (match_operand:BFP 2 "general_operand" "f,")) - (match_operand:BFP 3 "const0_operand" ""))) - (clobber (match_scratch:BFP 0 "=f,f"))] + (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%,0") + (match_operand:FP 2 "general_operand" " f,")) + (match_operand:FP 3 "const0_operand" ""))) + (clobber (match_scratch:FP 0 "=f,f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - abr\t%0,%2 + ar\t%0,%2 ab\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" ",RXE") + (set_attr "type" "fsimp")]) ; axr, adr, aer, ax, ad, ae (define_insn "*add3_ibm" @@ -4221,59 +4390,59 @@ [(set_attr "op_type" "RR,RX,RXY")]) ; -; sub(df|sf)3 instruction pattern(s). +; sub(tf|df|sf|td|dd)3 instruction pattern(s). ; (define_expand "sub3" [(parallel - [(set (match_operand:BFP 0 "register_operand" "=f,f") - (minus:BFP (match_operand:BFP 1 "register_operand" "0,0") - (match_operand:BFP 2 "general_operand" "f,R"))) + [(set (match_operand:FP 0 "register_operand" "") + (minus:FP (match_operand:FP 1 "register_operand" "") + (match_operand:FP 2 "general_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") -; sxbr, sdbr, sebr, sxb, sdb, seb +; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub3" - [(set (match_operand:BFP 0 "register_operand" "=f,f") - (minus:BFP (match_operand:BFP 1 "register_operand" "0,0") - (match_operand:BFP 2 "general_operand" "f,"))) + [(set (match_operand:FP 0 "register_operand" "=f, f") + (minus:FP (match_operand:FP 1 "register_operand" ",0") + (match_operand:FP 2 "general_operand" "f,"))) (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sbr\t%0,%2 + sr\t%0,%2 sb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" ",RXE") + (set_attr "type" "fsimp")]) -; sxbr, sdbr, sebr, sxb, sdb, seb +; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub3_cc" [(set (reg CC_REGNUM) - (compare (minus:BFP (match_operand:BFP 1 "nonimmediate_operand" "0,0") - (match_operand:BFP 2 "general_operand" "f,")) - (match_operand:BFP 3 "const0_operand" ""))) - (set (match_operand:BFP 0 "register_operand" "=f,f") - (minus:BFP (match_dup 1) (match_dup 2)))] + (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" ",0") + (match_operand:FP 2 "general_operand" "f,")) + (match_operand:FP 3 "const0_operand" ""))) + (set (match_operand:FP 0 "register_operand" "=f,f") + (minus:FP (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sbr\t%0,%2 + sr\t%0,%2 sb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" ",RXE") + (set_attr "type" "fsimp")]) -; sxbr, sdbr, sebr, sxb, sdb, seb +; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub3_cconly" [(set (reg CC_REGNUM) - (compare (minus:BFP (match_operand:BFP 1 "nonimmediate_operand" "0,0") - (match_operand:BFP 2 "general_operand" "f,")) - (match_operand:BFP 3 "const0_operand" ""))) - (clobber (match_scratch:BFP 0 "=f,f"))] + (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" ",0") + (match_operand:FP 2 "general_operand" "f,")) + (match_operand:FP 3 "const0_operand" ""))) + (clobber (match_scratch:FP 0 "=f,f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sbr\t%0,%2 + sr\t%0,%2 sb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" ",RXE") + (set_attr "type" "fsimp")]) ; sxr, sdr, ser, sx, sd, se (define_insn "*sub3_ibm" @@ -4531,27 +4700,27 @@ (set_attr "type" "imulsi")]) ; -; mul(df|sf)3 instruction pattern(s). +; mul(tf|df|sf|td|dd)3 instruction pattern(s). ; (define_expand "mul3" - [(set (match_operand:BFP 0 "register_operand" "=f,f") - (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0") - (match_operand:BFP 2 "general_operand" "f,")))] + [(set (match_operand:FP 0 "register_operand" "") + (mult:FP (match_operand:FP 1 "nonimmediate_operand" "") + (match_operand:FP 2 "general_operand" "")))] "TARGET_HARD_FLOAT" "") -; mxbr mdbr, meebr, mxb, mxb, meeb +; mxbr mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr (define_insn "*mul3" - [(set (match_operand:BFP 0 "register_operand" "=f,f") - (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0") - (match_operand:BFP 2 "general_operand" "f,")))] + [(set (match_operand:FP 0 "register_operand" "=f,f") + (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%,0") + (match_operand:FP 2 "general_operand" "f,")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - mbr\t%0,%2 + mr\t%0,%2 mb\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fmul")]) + [(set_attr "op_type" ",RXE") + (set_attr "type" "fmul")]) ; mxr, mdr, mer, mx, md, me (define_insn "*mul3_ibm" @@ -5014,23 +5183,23 @@ ; (define_expand "div3" - [(set (match_operand:BFP 0 "register_operand" "=f,f") - (div:BFP (match_operand:BFP 1 "register_operand" "0,0") - (match_operand:BFP 2 "general_operand" "f,")))] + [(set (match_operand:FP 0 "register_operand" "") + (div:FP (match_operand:FP 1 "register_operand" "") + (match_operand:FP 2 "general_operand" "")))] "TARGET_HARD_FLOAT" "") -; dxbr, ddbr, debr, dxb, ddb, deb +; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr (define_insn "*div3" - [(set (match_operand:BFP 0 "register_operand" "=f,f") - (div:BFP (match_operand:BFP 1 "register_operand" "0,0") - (match_operand:BFP 2 "general_operand" "f,")))] + [(set (match_operand:FP 0 "register_operand" "=f,f") + (div:FP (match_operand:FP 1 "register_operand" ",0") + (match_operand:FP 2 "general_operand" "f,")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - dbr\t%0,%2 + dr\t%0,%2 db\t%0,%2" - [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fdiv")]) + [(set_attr "op_type" ",RXE") + (set_attr "type" "fdiv")]) ; dxr, ddr, der, dx, dd, de (define_insn "*div3_ibm" @@ -6045,12 +6214,12 @@ ; lcdfr (define_insn "*neg2_nocc" - [(set (match_operand:BFP 0 "register_operand" "=f") - (neg:BFP (match_operand:BFP 1 "register_operand" "")))] + [(set (match_operand:FP 0 "register_operand" "=f") + (neg:FP (match_operand:FP 1 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_DFP" "lcdfr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimp")]) + (set_attr "type" "fsimp")]) ; lcxbr, lcdbr, lcebr (define_insn "*neg2" @@ -6168,12 +6337,12 @@ ; lpdfr (define_insn "*abs2_nocc" - [(set (match_operand:BFP 0 "register_operand" "=f") - (abs:BFP (match_operand:BFP 1 "register_operand" "")))] + [(set (match_operand:FP 0 "register_operand" "=f") + (abs:FP (match_operand:FP 1 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_DFP" "lpdfr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimp")]) + (set_attr "type" "fsimp")]) ; lpxbr, lpdbr, lpebr (define_insn "*abs2" @@ -6283,12 +6452,12 @@ ; lndfr (define_insn "*negabs2_nocc" - [(set (match_operand:BFP 0 "register_operand" "=f") - (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" ""))))] + [(set (match_operand:FP 0 "register_operand" "=f") + (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" ""))))] "TARGET_HARD_FLOAT && TARGET_DFP" "lndfr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimp")]) + (set_attr "type" "fsimp")]) ; lnxbr, lndbr, lnebr (define_insn "*negabs2" @@ -6306,14 +6475,14 @@ ; cpsdr (define_insn "copysign3" - [(set (match_operand:BFP 0 "register_operand" "=f") - (unspec:BFP [(match_operand:BFP 1 "register_operand" "") - (match_operand:BFP 2 "register_operand" "f")] + [(set (match_operand:FP 0 "register_operand" "=f") + (unspec:FP [(match_operand:FP 1 "register_operand" "") + (match_operand:FP 2 "register_operand" "f")] UNSPEC_COPYSIGN))] "TARGET_HARD_FLOAT && TARGET_DFP" "cpsdr\t%0,%2,%1" [(set_attr "op_type" "RRF") - (set_attr "type" "fsimp")]) + (set_attr "type" "fsimp")]) ;; ;;- Square root instructions.