From: Pan Li Date: Thu, 17 Aug 2023 02:04:51 +0000 (+0800) Subject: RISC-V: Support RVV VFNCVT.F.{X|XU|F}.W rounding mode intrinsic API X-Git-Tag: basepoints/gcc-15~6867 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=20e1db413ee8bb4d5233d97484e19e4e1d85f4ac;p=thirdparty%2Fgcc.git RISC-V: Support RVV VFNCVT.F.{X|XU|F}.W rounding mode intrinsic API This patch would like to support the rounding mode API for the VFNCVT.F.{X|XU|F}.W as the below samples. * __riscv_vfncvt_f_x_w_f32m1_rm * __riscv_vfncvt_f_x_w_f32m1_rm_m * __riscv_vfncvt_f_xu_w_f32m1_rm * __riscv_vfncvt_f_xu_w_f32m1_rm_m * __riscv_vfncvt_f_f_w_f32m1_rm * __riscv_vfncvt_f_f_w_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfncvt_f): Add frm_op_type template arg. (vfncvt_f_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfncvt_f_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-ncvt-f.c: New test. --- diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index acadec2afca7..ad04647f9ba5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1786,9 +1786,15 @@ public: } }; +template class vfncvt_f : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_f_w) @@ -2512,7 +2518,8 @@ static CONSTEXPR const vfncvt_x vfncvt_xu_obj; static CONSTEXPR const vfncvt_x vfncvt_xu_frm_obj; static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj; static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj; -static CONSTEXPR const vfncvt_f vfncvt_f_obj; +static CONSTEXPR const vfncvt_f vfncvt_f_obj; +static CONSTEXPR const vfncvt_f vfncvt_f_frm_obj; static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj; static CONSTEXPR const reducop vredsum_obj; static CONSTEXPR const reducop vredmaxu_obj; @@ -2769,6 +2776,7 @@ BASE (vfncvt_xu_frm) BASE (vfncvt_rtz_x) BASE (vfncvt_rtz_xu) BASE (vfncvt_f) +BASE (vfncvt_f_frm) BASE (vfncvt_rod_f) BASE (vredsum) BASE (vredmaxu) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 9bd09a419603..c8c649c4bb0d 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -226,6 +226,7 @@ extern const function_base *const vfncvt_xu_frm; extern const function_base *const vfncvt_rtz_x; extern const function_base *const vfncvt_rtz_xu; extern const function_base *const vfncvt_f; +extern const function_base *const vfncvt_f_frm; extern const function_base *const vfncvt_rod_f; extern const function_base *const vredsum; extern const function_base *const vredmaxu; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 1e0e989fc2ad..cfbc125dcd8b 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -474,6 +474,9 @@ DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds, f_to_nf_f_w_ops) DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops) DEF_RVV_FUNCTION (vfncvt_xu_frm, narrow_alu_frm, full_preds, f_to_nu_f_w_ops) +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, i_to_nf_x_w_ops) +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, u_to_nf_xu_w_ops) +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, f_to_nf_f_w_ops) /* 14. Vector Reduction Operations. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c new file mode 100644 index 000000000000..d6d4be5e98ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t +test_riscv_vfncvt_f_x_w_f32m1_rm (vint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_vfncvt_f_x_w_f32m1_rm_m (vbool32_t mask, vint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1_rm_m (mask, op1, 1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_xu_w_f32m1_rm (vuint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_vfncvt_f_xu_w_f32m1_rm_m (vbool32_t mask, vuint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1_rm_m (mask, op1, 1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_f_w_f32m1_rm (vfloat64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_vfncvt_f_f_w_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1_rm_m (mask, op1, 1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_x_w_f32m1 (vint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfncvt_f_x_w_f32m1_m (vbool32_t mask, vint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1_m (mask, op1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_xu_w_f32m1 (vuint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfncvt_f_xu_w_f32m1_m (vbool32_t mask, vuint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1_m (mask, op1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_f_w_f32m1 (vfloat64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfncvt_f_f_w_f32m1_m (vbool32_t mask, vfloat64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfncvt\.f\.[xuf]+\.w\s+v[0-9]+,\s*v[0-9]+} 12 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 6 } } */