From: Jakub Jelinek Date: Mon, 7 Mar 2022 10:14:04 +0000 (+0100) Subject: s390: Fix up *cmp_and_trap_unsigned_int constraints [PR104775] X-Git-Tag: releases/gcc-10.4.0~180 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2183785c198ef17138985509cedf5051b3d58452;p=thirdparty%2Fgcc.git s390: Fix up *cmp_and_trap_unsigned_int constraints [PR104775] The following testcase fails to assemble due to clgte %r6,0(%r1,%r10) insn not being accepted by assembler. My rough understanding is that in the RSY-b insn format the spot in other formats used for index registers is used instead for M3 what kind of comparison it is, so this patch follows what other similar instructions use for constraint (i.e. one without index register). 2022-03-07 Jakub Jelinek PR target/104775 * config/s390/s390.md (*cmp_and_trap_unsigned_int): Use S constraint instead of T in the last alternative. * gcc.target/s390/pr104775.c: New test. (cherry picked from commit 2472dcaa8cb9e02e902f83d419c3ee7e0f3d9041) --- diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 4039107a7bea..2fc4924f59f2 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -9474,7 +9474,7 @@ (define_insn "*cmp_and_trap_unsigned_int" [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" [(match_operand:GPR 1 "register_operand" "d,d,d") - (match_operand:GPR 2 "general_operand" "d,D,T")]) + (match_operand:GPR 2 "general_operand" "d,D,S")]) (const_int 0))] "TARGET_Z10" "@ diff --git a/gcc/testsuite/gcc.target/s390/pr104775.c b/gcc/testsuite/gcc.target/s390/pr104775.c new file mode 100644 index 000000000000..fd4258bb36f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr104775.c @@ -0,0 +1,14 @@ +/* PR target/104775 */ +/* { dg-do assemble { target s390_zEC12_hw } } */ +/* { dg-options "-O2 -march=zEC12" } */ + +long a[64]; +void bar (void); + +void +foo (int x, int y) +{ + if (x != a[y]) + bar (); + __builtin_trap (); +}